| .. |
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arm64-atomic-128.ll
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AArch64: use indivisible cmpxchg for 128-bit atomic loads at O0
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2021-09-22 14:20:43 +01:00 |
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arm64-atomic.ll
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[AArch64] Make -mcpu=generic schedule for an in-order core
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2021-10-09 15:58:31 +01:00 |
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arm64-callingconv-ios.ll
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Delay outgoing register assignments to last.
|
2021-10-04 12:33:20 -07:00 |
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arm64-callingconv.ll
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Delay outgoing register assignments to last.
|
2021-10-04 12:33:20 -07:00 |
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arm64-fallback.ll
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[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
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2022-01-06 14:23:51 +01:00 |
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arm64-irtranslator-fmuladd.ll
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…
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arm64-irtranslator-gep.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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arm64-irtranslator-stackprotect.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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arm64-irtranslator-switch.ll
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[AArch64] Emit AssertZExt for i1 arguments
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2021-10-11 11:55:11 +03:00 |
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arm64-irtranslator.ll
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[AArch64] Emit AssertZExt for i1 arguments
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2021-10-11 11:55:11 +03:00 |
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arm64-regbankselect.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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artifact-combine-unmerge.mir
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…
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artifact-find-value.mir
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[GlobalISel] Improve elimination of dead instructions in legalizer
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2021-09-20 13:00:58 +02:00 |
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assert-align.ll
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Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
|
2022-01-24 09:26:52 -05:00 |
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builtin-return-address-pacret.ll
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Reapply "RegAllocFast: Rewrite and improve"
|
2020-09-30 10:35:25 -04:00 |
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byval-call.ll
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[AArch64] Make -mcpu=generic schedule for an in-order core
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2021-10-09 15:58:31 +01:00 |
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call-lowering-const-bitcast-func.ll
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…
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call-lowering-i128-on-stack.ll
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…
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call-lowering-i256-crash.ll
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…
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call-lowering-signext.ll
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[AArch64] Emit AssertZExt for i1 arguments
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2021-10-11 11:55:11 +03:00 |
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call-lowering-vectors.ll
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[GlobalISel] Rework more/fewer elements for vectors
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2021-12-23 14:30:02 +01:00 |
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call-lowering-zeroext.ll
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[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
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2021-08-02 14:48:44 -07:00 |
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call-translator-cse.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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call-translator-ios.ll
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[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
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2021-08-02 14:48:44 -07:00 |
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call-translator-musttail.ll
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…
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call-translator-tail-call-sret.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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call-translator-tail-call-weak.ll
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[NFC] Removed unused prefixes in llvm/test/CodeGen/AArch64
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2020-12-09 12:47:51 -08:00 |
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call-translator-tail-call.ll
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Delay outgoing register assignments to last.
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2021-10-04 12:33:20 -07:00 |
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call-translator-variadic-musttail.ll
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[AArch64] Make -mcpu=generic schedule for an in-order core
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2021-10-09 15:58:31 +01:00 |
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call-translator.ll
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[AArch64] Emit AssertZExt for i1 arguments
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2021-10-11 11:55:11 +03:00 |
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combine-and-or-disjoint-mask.mir
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[AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0
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2021-10-20 12:11:52 -07:00 |
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combine-anyext-crash.mir
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…
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combine-build-vector.mir
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[GlobalISel] Fold away G_BUILD_VECTOR with all elements extracted.
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2021-03-09 11:34:26 -08:00 |
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combine-copy.mir
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…
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combine-ext-debugloc.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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combine-ext.mir
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GlobalISel: Add combines for extend operations
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2020-09-01 08:50:06 -07:00 |
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combine-extract-vec-elt.mir
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[AArch64][GlobalISel] Add combine for extract_vector_elt(build_vector, cst)
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2021-03-09 11:08:02 -08:00 |
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combine-fabs.mir
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[GISel] Add new combines for unary FP instrs with constant operand
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2020-09-16 10:34:15 -07:00 |
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combine-fconstant.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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combine-flog2.mir
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[GISel] Add new combines for unary FP instrs with constant operand
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2020-09-16 10:34:15 -07:00 |
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combine-fneg.mir
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[GISel] Add new combines for unary FP instrs with constant operand
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2020-09-16 10:34:15 -07:00 |
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combine-fptrunc.mir
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[GISel] Add new combines for unary FP instrs with constant operand
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2020-09-16 10:34:15 -07:00 |
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combine-fsqrt.mir
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[GISel] Add new combines for unary FP instrs with constant operand
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2020-09-16 10:34:15 -07:00 |
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combine-icmp-to-lhs-known-bits.mir
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Add missing `REQUIRES: asserts` to combine-icmp-to-lhs-known-bits.mir
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2021-09-03 09:25:37 -07:00 |
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combine-insert-vec-elt.mir
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[GISel]: Few InsertVecElt combines
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2020-10-28 12:27:07 -07:00 |
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combine-inttoptr-ptrtoint.mir
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[GISel] Add combiners for G_INTTOPTR and G_PTRTOINT
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2020-07-31 10:13:36 -07:00 |
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combine-mul-to-shl.mir
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…
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combine-mul.mir
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[GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat vectors.
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2021-09-30 14:31:25 -07:00 |
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combine-mulo-with-2.mir
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[GlobalISel] Combine mulo x, 2 -> addo x, x
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2021-09-28 16:59:43 -07:00 |
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combine-ptradd-int2ptr.mir
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[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
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2022-01-20 17:02:52 +00:00 |
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combine-ptradd-reassociation.mir
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[GlobalISel] Make G_PTR_ADD pattern matcher non-commutative.
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2021-12-09 12:38:16 -08:00 |
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combine-ptrtoint.mir
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[GISel] Add combiners for G_INTTOPTR and G_PTRTOINT
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2020-07-31 10:13:36 -07:00 |
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combine-select.mir
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[GlobalISel] Extend G_SELECT of known condition combine to vectors.
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2021-09-30 12:16:44 -07:00 |
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combine-sext-debugloc.mir
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…
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combine-sext-trunc-sextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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combine-shift-immed-mismatch-crash.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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combine-shift-of-shifted-dbg-value-fallback.ll
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[GlobalISel] Fix a combine causing DBG_VALUE with dangling vregs.
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2021-08-07 01:41:02 -07:00 |
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combine-shl.mir
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GlobalISel: Combine `op undef, x` to 0
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2020-09-08 09:46:38 -07:00 |
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combine-trunc.mir
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GlobalISel: Fix truncating shift amount in trunc (shl) combine
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2020-09-23 09:07:50 -04:00 |
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combine-udiv.ll
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[SchedModels][CortexA55] Add ASIMD integer instructions
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2022-02-17 13:41:57 +03:00 |
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combine-udiv.mir
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[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.
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2021-10-12 11:31:22 -07:00 |
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combine-umulh-to-lshr.mir
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[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.
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2021-10-12 11:31:22 -07:00 |
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combine-unmerge.mir
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[GlobalISel] Add a `X, Y = G_UNMERGE(G_ZEXT Z)` -> X = G_ZEXT Z; Y = 0 combine
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2020-09-14 17:27:23 -07:00 |
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combiner-load-store-indexing.ll
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…
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constant-dbg-loc.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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constant-mir-debugify.mir
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[DIBuilder] Do not replace empty enum types
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2021-08-30 12:33:03 -07:00 |
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contract-store.mir
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[AArch64] Rename CPY to DUP. NFC
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2022-01-05 20:02:39 +00:00 |
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darwin-tls-call-clobber.ll
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Reapply "RegAllocFast: Rewrite and improve"
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2020-09-30 10:35:25 -04:00 |
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debug-cpp.ll
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…
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debug-insts.ll
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…
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debug-loc-legalize-tail-call.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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dynamic-alloca-lifetime.ll
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…
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dynamic-alloca.ll
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…
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fallback-nofastisel.ll
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…
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fconstant-dbg-loc.ll
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…
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fold-brcond-fcmp.mir
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[GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs
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2020-10-01 15:34:16 -07:00 |
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fold-fp-select.mir
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[AArch64][GlobalISel] Don't use explicit zero registers for compare results.
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2020-10-14 16:49:33 -07:00 |
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fold-global-offsets-target-features.mir
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Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
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2021-03-18 16:01:02 -07:00 |
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fold-global-offsets.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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fold-select.mir
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[AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering
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2020-10-22 15:27:36 -07:00 |
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form-bitfield-extract-from-and.mir
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[GlobalISel][AArch64] Combine and (lshr x, cst), mask -> ubfx x, cst, width
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2021-06-01 10:56:17 -07:00 |
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form-bitfield-extract-from-sextinreg.mir
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[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
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2021-04-29 21:54:19 -04:00 |
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form-bitfield-extract-from-shr-and.mir
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[AArch64][GlobalISel] combine and + [la]sr => ubfx
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2021-10-18 10:33:01 -07:00 |
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form-bitfield-extract-from-shr.mir
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[GlobalISel] Combine shr(shl x, c1), c2 to G_SBFX/G_UBFX
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2021-08-05 13:52:10 +02:00 |
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fp16-copy-gpr.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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fp128-legalize-crash-pr35690.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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freeze.ll
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[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
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2021-08-03 02:28:46 -07:00 |
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gisel-abort.ll
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…
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gisel-commandline-option-fastisel.ll
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…
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gisel-commandline-option.ll
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GlobalISel: Always enable GISelKnownBits for InstructionSelect
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2022-01-12 18:57:24 -05:00 |
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gisel-fail-intermediate-legalizer.ll
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…
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huge-switch.ll
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GlobalISel: check type size before getZExtValue()ing it.
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2021-02-01 12:43:33 +00:00 |
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implicit_def_rbs_crash.mir
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[GlobalISel] Fix crash in RBS with a non-generic IMPLICIT_DEF.
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2021-03-24 23:08:51 -07:00 |
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inline-asm.ll
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…
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inline-memcpy-forced.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inline-memcpy.mir
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GlobalISel: remove assert that memcpy Src and Dst addrspace must be identical
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2021-11-24 20:23:05 -05:00 |
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inline-memmove.mir
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GlobalISel: remove assert that memcpy Src and Dst addrspace must be identical
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2021-11-24 20:23:05 -05:00 |
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inline-memset.mir
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GlobalISel: Preserve memory type for memset expansion
|
2021-07-16 11:41:32 -04:00 |
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inline-small-memcpy.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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integration-shuffle-vector.ll
|
…
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inttoptr_add.ll
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[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
|
2022-01-20 17:02:52 +00:00 |
|
irtranslator-arguments.ll
|
Delay outgoing register assignments to last.
|
2021-10-04 12:33:20 -07:00 |
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irtranslator-atomic-metadata.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-bitcast.ll
|
…
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|
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irtranslator-block-order.ll
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…
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irtranslator-condbr-lower-tree.ll
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[SimplifyCFG] Tail-merging all blocks with `ret` terminator
|
2021-06-24 13:15:39 +03:00 |
|
irtranslator-convert-fp16-intrinsics.ll
|
…
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|
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irtranslator-delayed-stack-protector.ll
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[GlobalISel] Port over the SelectionDAG stack protector codegen feature.
|
2021-10-04 21:33:44 -07:00 |
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irtranslator-dilocation.ll
|
…
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|
|
irtranslator-duplicate-types-param.ll
|
…
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|
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irtranslator-exceptions.ll
|
Delay outgoing register assignments to last.
|
2021-10-04 12:33:20 -07:00 |
|
irtranslator-extends.ll
|
…
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|
|
irtranslator-extract-used-by-dbg.ll
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[[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a non-dominated metadata use.
|
2020-12-12 14:58:54 -08:00 |
|
irtranslator-fixed-point-intrinsics.ll
|
…
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|
|
irtranslator-fp-min-max-intrinsics.ll
|
…
|
|
|
irtranslator-indirect-br-repeated-block.ll
|
…
|
|
|
irtranslator-inline-asm.ll
|
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
|
2022-01-06 14:23:51 +01:00 |
|
irtranslator-invoke-probabilities.ll
|
[CodeGen] Add "noreturn" attirbute to _Unwind_Resume
|
2020-12-24 18:14:18 +07:00 |
|
irtranslator-load-metadata.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-localescape.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-max-address-space.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-memcpy-inline.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-memfunc-undef.ll
|
…
|
|
|
irtranslator-no-op-intrinsics.ll
|
Try to fix buildbots after d3205bbca3
|
2020-10-26 11:49:21 +01:00 |
|
irtranslator-no-unwind-inline-asm.ll
|
Support unwinding from inline assembly
|
2021-05-13 19:13:03 +01:00 |
|
irtranslator-one-by-n-vector-ptr-add.ll
|
[GlobalISel] Translate <1 x N> getelementptrs to scalar G_PTR_ADDs
|
2021-07-01 16:38:47 -07:00 |
|
irtranslator-reductions.ll
|
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
|
2021-05-05 17:35:02 -04:00 |
|
irtranslator-split-vector-arg.ll
|
…
|
|
|
irtranslator-stack-evt-bug47619.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-stack-objects.ll
|
[CallLowering] Support opaque pointers
|
2021-09-10 18:32:12 +02:00 |
|
irtranslator-store-metadata.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-switch-bittest.ll
|
[GlobalISel][IRTranslator] Fix crash during bit-test switch optimization with odd types.
|
2021-09-24 00:19:27 -07:00 |
|
irtranslator-tbaa.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-unreachable.ll
|
Revert "Revert "[GlobalISel][IRTranslator] Emit trap intrinsic for "unreachable"""
|
2021-10-06 04:16:19 -07:00 |
|
irtranslator-unwind-inline-asm.ll
|
[GlobalISel] Ensure that translateInvoke adds all successors for inlineasm
|
2021-11-09 16:20:34 -08:00 |
|
irtranslator-volatile-load-pr36018.ll
|
…
|
|
|
irtranslator-weird-alloca-size.ll
|
…
|
|
|
labels-are-not-dead.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-abs.mir
|
[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
|
2021-04-21 18:10:40 -07:00 |
|
legalize-add.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-and.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-atomicrmw.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-bitreverse.mir
|
[AArch64][GlobalISel] Legalize non-register-sized scalar G_BITREVERSE
|
2021-08-20 14:44:03 -07:00 |
|
legalize-blockaddress.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-bswap.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-build-vector.mir
|
[AArch64][GlobalISel] Widen G_BUILD_VECTOR source & dest element types to s8.
|
2021-09-29 15:11:30 -07:00 |
|
legalize-bzero-unsupported.mir
|
[AArch64][GlobalISel] Emit bzero on Darwin
|
2021-03-25 17:14:25 -07:00 |
|
legalize-bzero.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-ceil.mir
|
…
|
|
|
legalize-cmp.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-cmpxchg-128.mir
|
AArch64: do not use xzr for ldxp -> stxp dataflow.
|
2022-02-09 12:29:16 +00:00 |
|
legalize-cmpxchg-with-success.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-cmpxchg.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-combines.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-concat-vectors.mir
|
[AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal
|
2021-08-05 09:40:46 -07:00 |
|
legalize-constant.mir
|
[AArch64][GlobalISel] Improve legalization for odd-sized G_ICMP/G_CONSTANT
|
2021-07-28 15:31:33 -07:00 |
|
legalize-cos.mir
|
…
|
|
|
legalize-ctlz.mir
|
[AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
|
2021-03-23 12:49:10 -07:00 |
|
legalize-ctpop-no-implicit-float.mir
|
[AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP
|
2021-04-19 10:56:02 -07:00 |
|
legalize-ctpop.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-cttz-zero-undef.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-cttz.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-div.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-divrem.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-dyn-alloca.mir
|
…
|
|
|
legalize-exceptions.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-exp.mir
|
…
|
|
|
legalize-ext-cse.mir
|
…
|
|
|
legalize-ext-csedebug-output.mir
|
GlobalISel: Do not set observer of MachineIRBuilder in LegalizerHelper
|
2021-01-13 10:44:31 -05:00 |
|
legalize-ext.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-extload.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-extract-vector-elt.mir
|
[GlobalISel] Widen G_EXTRACT_VECTOR_ELT using anyext instead of sext.
|
2021-10-04 12:19:19 -07:00 |
|
legalize-extracts.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-fcmp.mir
|
…
|
|
|
legalize-fexp2.mir
|
…
|
|
|
legalize-fma.mir
|
…
|
|
|
legalize-fmaximum.mir
|
[AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM
|
2021-12-09 11:54:14 -08:00 |
|
legalize-fmaxnum.mir
|
[AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
|
2021-08-18 13:30:03 -07:00 |
|
legalize-fminimum.mir
|
[AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM
|
2021-12-09 11:54:14 -08:00 |
|
legalize-fminnum.mir
|
[AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
|
2021-08-18 13:30:03 -07:00 |
|
legalize-fp-arith-fp16.mir
|
[AArch64][GlobalISel] Legalize narrow scalar FP arithmetic
|
2021-08-24 13:54:28 -07:00 |
|
legalize-fp-arith.mir
|
[AArch64][GlobalISel] Clamp oversize FP arithmetic vectors.
|
2020-09-30 18:03:37 -07:00 |
|
legalize-fp16-fconstant.mir
|
[AArch64][GlobalISel] Mark G_FCONSTANT as legal when there is full fp16 support
|
2020-11-11 13:25:11 -08:00 |
|
legalize-fp128-fconstant.mir
|
[AArch64][GlobalISel] Add support for FCONSTANT of FP128 type
|
2021-01-13 10:46:10 -05:00 |
|
legalize-fpext.mir
|
GlobalISel: Preserve memory type when reducing load/store width
|
2021-06-30 17:05:29 -04:00 |
|
legalize-fptoi.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-fptrunc.mir
|
GlobalISel: Preserve memory type when reducing load/store width
|
2021-06-30 17:05:29 -04:00 |
|
legalize-freeze.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-frint.mir
|
…
|
|
|
legalize-fshl.mir
|
[AArch64][GlobalISel] Lower G_FSHL and G_FSHR.
|
2021-03-23 16:09:19 -07:00 |
|
legalize-fshr.mir
|
[AArch64][GlobalISel] Add test for G_FSHR legalization.
|
2021-03-23 16:11:45 -07:00 |
|
legalize-global-pic.mir
|
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
|
2021-03-18 16:01:02 -07:00 |
|
legalize-global.mir
|
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
|
2021-03-18 16:01:02 -07:00 |
|
legalize-ignore-hint.mir
|
[GlobalISel] Add G_ASSERT_ZEXT
|
2021-01-28 13:58:37 -08:00 |
|
legalize-ignore-non-generic.mir
|
…
|
|
|
legalize-insert-vector-elt.mir
|
[AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal.
|
2020-09-25 01:59:16 -07:00 |
|
legalize-inserts.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-intrinsic-get-dynamic-area-offset.mir
|
[AArch64][GlobalISel] Add legalizer support for the @llvm.get.dynamic.area.offset intrinsic.
|
2021-08-20 17:13:34 -07:00 |
|
legalize-intrinsic-min-max.mir
|
[AArch64][GlobalISel] Lower scalar G_{SMIN, SMAX, UMIN, UMAX}.
|
2021-03-09 10:03:16 -08:00 |
|
legalize-intrinsic-round.mir
|
…
|
|
|
legalize-intrinsic-trunc.mir
|
…
|
|
|
legalize-inttoptr-xfail-1.mir
|
…
|
|
|
legalize-inttoptr-xfail-2.mir
|
…
|
|
|
legalize-inttoptr.mir
|
[AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal
|
2021-07-13 17:28:14 -07:00 |
|
legalize-itofp.mir
|
[AArch64][GlobalISel] Widen G_BUILD_VECTOR source & dest element types to s8.
|
2021-09-29 15:11:30 -07:00 |
|
legalize-llround.mir
|
[AArch64][GlobalISel] Legalize G_LLROUND for s64 + s32
|
2021-08-23 09:45:23 -07:00 |
|
legalize-load-store-fewerElts.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-load-store-vector-of-ptr-debugloc.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-load-store-vector-of-ptr.mir
|
AArch64/GlobalISel: Preserve memory types
|
2021-07-19 20:21:05 -04:00 |
|
legalize-load-store.mir
|
[GlobalISel][Legalizer] Use ArtifactValueFinder first for unmerge combines before trying others.
|
2021-09-21 00:02:15 -07:00 |
|
legalize-load-trunc.mir
|
GlobalISel: Use LLT in memory legality queries
|
2021-06-30 17:44:13 -04:00 |
|
legalize-log.mir
|
…
|
|
|
legalize-log2.mir
|
…
|
|
|
legalize-log10.mir
|
…
|
|
|
legalize-lrint.mir
|
[AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT.
|
2020-07-30 16:14:56 -07:00 |
|
legalize-lround.mir
|
[AArch64][GlobalISel] Mark G_LROUND as legal for s64 dst + s32/s64 src.
|
2021-08-20 14:22:58 -07:00 |
|
legalize-memcpy-et-al.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-memcpy-with-debug-info.mir
|
[llvm] Inclusive language: replace master with main in file paths in LIT tests
|
2021-11-08 12:39:50 -06:00 |
|
legalize-memlib-debug-loc.mir
|
[GlobalISel] Mark memcpy/memmove/memset as thisreturn
|
2021-07-20 17:04:33 -07:00 |
|
legalize-merge-values.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-min-max.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-mul.mir
|
[AArch64][GlobalISel] Lower G_SMULH/G_UMULH unless its one of the supported types.
|
2021-10-01 22:15:23 -07:00 |
|
legalize-nearbyint.mir
|
…
|
|
|
legalize-non-pow2-load-store.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-or.mir
|
…
|
|
|
legalize-phi-insertpt-decrement.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-phi.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-pow.mir
|
…
|
|
|
legalize-property.mir
|
…
|
|
|
legalize-ptr-add.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-ptrtoint.mir
|
[AArch64][GlobalISel] Legalize + select v2p0 -> v264 G_PTRTOINT
|
2021-08-24 11:02:01 -07:00 |
|
legalize-reduce-add.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-reduce-and.mir
|
[AArch64][GlobalISel] Legalize G_VECREDUCE_AND.
|
2021-10-05 00:39:29 -07:00 |
|
legalize-reduce-fadd.mir
|
[GlobalISel] Implement fewerElements legalization for vector reductions.
|
2021-03-30 11:19:21 -07:00 |
|
legalize-reduce-or.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-reduce-xor.mir
|
[AArch64][GlobalISel] Legalize G_VECREDUCE_XOR. Treated same as other bitwise reductions.
|
2021-10-10 17:01:21 -07:00 |
|
legalize-rem.mir
|
AArch64+GISel: legalize vector remainder operations.
|
2021-10-05 10:20:10 +01:00 |
|
legalize-rotr-rotl.mir
|
[AArch64][GlobalISel] Define some legalization rules for G_ROTR and G_ROTL.
|
2021-03-30 11:11:19 -07:00 |
|
legalize-s128-div.mir
|
Delay outgoing register assignments to last.
|
2021-10-04 12:33:20 -07:00 |
|
legalize-sadde.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-saddo.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-saddsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sbfx.mir
|
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
|
2021-04-02 11:11:06 -04:00 |
|
legalize-select.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-sext-128.ll
|
…
|
|
|
legalize-sext-128.mir
|
…
|
|
|
legalize-sext-copy.mir
|
…
|
|
|
legalize-sext-zext-128.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-sext.mir
|
…
|
|
|
legalize-sextload.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-shift-imm-promote-dloc.mir
|
…
|
|
|
legalize-shift.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-shuffle-vector.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-simple.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-sin.mir
|
…
|
|
|
legalize-sqrt.mir
|
…
|
|
|
legalize-ssube.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-ssubo.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-ssubsat.mir
|
[GlobalISel] Rework more/fewer elements for vectors
|
2021-12-23 14:30:02 +01:00 |
|
legalize-sub.mir
|
[Test][AArch64] Move overflow add/sub tests to their own file. NFC
|
2021-01-25 22:02:31 -05:00 |
|
legalize-uadd-sat.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-uadde.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-uaddo.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-ubfx.mir
|
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
|
2021-04-02 11:11:06 -04:00 |
|
legalize-undef.mir
|
[AArch64][GlobalISel] Widen G_IMPLICIT_DEF and G_FREEZE before clamping
|
2021-08-05 18:21:14 -07:00 |
|
legalize-unmerge-values.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-usub-sat.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-usube.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-usubo.mir
|
[GlobalISel] Improve elimination of dead instructions in legalizer
|
2021-09-20 13:00:58 +02:00 |
|
legalize-vaarg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-vacopy.mir
|
AArch64: support @llvm.va_copy in GISel
|
2021-08-10 13:11:03 +01:00 |
|
legalize-vector-cmp.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalize-vector-shift.mir
|
…
|
|
|
legalize-xor.mir
|
…
|
|
|
legalize-zextload.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalizer-combiner-zext-trunc-crash.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalizer-combiner.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
legalizer-info-validation.mir
|
[AMDGPU] Add a new intrinsic to control fp_trunc rounding mode
|
2022-02-11 12:08:23 -05:00 |
|
lifetime-marker-no-dce.mir
|
[GlobalISel] Don't DCE LIFETIME_START/LIFETIME_END markers.
|
2021-03-17 18:02:08 -07:00 |
|
load-addressing-modes.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
load-wro-addressing-modes.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
localizer-arm64-tti.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
localizer-in-O0-pipeline.mir
|
…
|
|
|
localizer.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
lower-neon-vector-fcmp.mir
|
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
|
2021-05-10 15:40:06 -07:00 |
|
machine-cse-mid-pipeline.mir
|
…
|
|
|
memcpy_chk_no_tail.ll
|
…
|
|
|
merge-stores-truncating.ll
|
[AArch64][GlobalISel] combine and + [la]sr => ubfx
|
2021-10-18 10:33:01 -07:00 |
|
merge-stores-truncating.mir
|
[GlobalISel] Fix the stores of truncates -> wide store combine for non-evenly dividing type sizes.
|
2021-10-09 21:18:20 -07:00 |
|
no-neon-no-fp.ll
|
[AArch64][GlobalISel] Fall back if disabling neon/fp in the translator.
|
2021-03-17 15:08:08 -07:00 |
|
no-regclass.mir
|
…
|
|
|
non-pow-2-extload-combine.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
observer-change-crash.mir
|
…
|
|
|
opt-and-tbnz-tbz.mir
|
[AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z
|
2020-12-01 15:45:14 -08:00 |
|
opt-fold-and-tbz-tbnz.mir
|
…
|
|
|
opt-fold-compare.mir
|
[AArch64][GlobalISel] Don't explicitly write to the zero register in emitCMN
|
2020-12-08 10:42:05 -08:00 |
|
opt-fold-ext-tbz-tbnz.mir
|
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
|
2021-05-18 10:00:00 -07:00 |
|
opt-fold-shift-tbz-tbnz.mir
|
…
|
|
|
opt-fold-trunc-tbz-tbnz.mir
|
…
|
|
|
opt-fold-xor-tbz-tbnz.mir
|
[AArch64][GlobalISel] Use ZExtValue for zext(xor) when invert tb(n)z
|
2021-09-06 11:12:07 +08:00 |
|
opt-overlapping-and-postlegalize.mir
|
[AArch64][GlobalISel] Run overlapping_and after legalization
|
2021-09-28 17:13:34 -07:00 |
|
opt-overlapping-and.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
opt-shifted-reg-compare.mir
|
[AArch64][GlobalISel] Don't use explicit zero registers for compare results.
|
2020-10-14 16:49:33 -07:00 |
|
phi-mir-debugify.mir
|
[DIBuilder] Do not replace empty enum types
|
2021-08-30 12:33:03 -07:00 |
|
postlegalizer-combine-ptr-add-chain.mir
|
[AArch64][GlobalISel] Add ptradd_immed_chain combine to post-legalizer combiner.
|
2021-08-11 13:59:23 -07:00 |
|
postlegalizer-combiner-and-trivial-mask.mir
|
[GlobalISel] Implement computeKnownBits for G_ASSERT_ZEXT
|
2021-01-28 16:34:34 -08:00 |
|
postlegalizer-combiner-anyext-to-zext.mir
|
[AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT
|
2021-10-01 15:01:20 -07:00 |
|
postlegalizer-combiner-constant-fold.mir
|
[GlobalISel] Add a constant folding combine.
|
2021-07-26 14:53:33 -07:00 |
|
postlegalizer-combiner-copy-prop.mir
|
[GlobalISel] Enable copy-propagation in post-legalizer combiner.
|
2020-08-15 13:44:30 -07:00 |
|
postlegalizer-combiner-identity.mir
|
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
|
2021-07-26 15:17:11 -07:00 |
|
postlegalizer-combiner-merge.mir
|
[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.
|
2021-07-26 10:58:04 -07:00 |
|
postlegalizer-combiner-redundant-sextinreg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postlegalizer-combiner-split-zero-stores.mir
|
AArch64/GlobalISel: Fix memory type in test
|
2021-12-20 19:11:48 -05:00 |
|
postlegalizer-combiner-store-undef.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postlegalizer-lowering-adjust-icmp-imm.mir
|
[AArch64][GlobalISel] Move imm adjustment for G_ICMP to post-legalizer lowering
|
2020-10-22 15:27:36 -07:00 |
|
postlegalizer-lowering-build-vector-to-dup.mir
|
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
|
2021-03-08 13:01:10 -08:00 |
|
postlegalizer-lowering-ext.mir
|
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
|
2020-10-22 14:43:25 -07:00 |
|
postlegalizer-lowering-rev.mir
|
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
|
2020-10-22 14:43:25 -07:00 |
|
postlegalizer-lowering-shuf-to-ins.mir
|
Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt"
|
2021-02-23 11:55:16 -08:00 |
|
postlegalizer-lowering-shuffle-duplane.mir
|
[AArch64][GlobalISel] Form G_DUPLANE32 for <2 x s32> shufflevectors in lowering.
|
2021-03-09 11:36:26 -08:00 |
|
postlegalizer-lowering-shuffle-splat.mir
|
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
|
2020-10-22 14:43:25 -07:00 |
|
postlegalizer-lowering-swap-compare-operands.mir
|
[AArch64][GlobalISel] Swap compare operands when it may be profitable
|
2021-04-09 15:46:48 -07:00 |
|
postlegalizer-lowering-trn.mir
|
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
|
2020-10-22 14:43:25 -07:00 |
|
postlegalizer-lowering-truncstore.mir
|
[AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128.
|
2021-07-20 00:04:34 -07:00 |
|
postlegalizer-lowering-uzp.mir
|
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
|
2020-10-22 14:43:25 -07:00 |
|
postlegalizer-lowering-vashr-vlshr.mir
|
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
|
2021-03-08 13:01:10 -08:00 |
|
postlegalizer-lowering-zip.mir
|
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
|
2020-10-22 14:43:25 -07:00 |
|
postlegalizercombiner-extending-loads.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postlegalizercombiner-extractvec-faddp.mir
|
[AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD.
|
2020-11-03 17:25:14 -08:00 |
|
postlegalizercombiner-hoist-same-hands.mir
|
[GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
|
2020-08-11 10:40:06 -07:00 |
|
postlegalizercombiner-mulpow2.mir
|
[AArch64][GlobalISel] Don't perform the mul const combine with G_PTR_ADD
|
2021-02-10 15:30:45 -08:00 |
|
postlegalizercombiner-rotate.mir
|
[GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero
|
2021-09-08 10:09:02 -07:00 |
|
postlegalizercombiner-select.mir
|
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
|
2021-07-26 15:17:11 -07:00 |
|
postselectopt-constrain-new-regop.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postselectopt-dead-cc-defs-in-fcmp.mir
|
[AArch64][GlobalISel] Introduce a new post-isel optimization pass.
|
2020-10-23 10:18:36 -07:00 |
|
prelegalizer-combiner-addo-zero.mir
|
[GlobalISel] Combine (G_*ADDO x, 0) -> x + no carry out
|
2022-02-03 14:25:15 -08:00 |
|
prelegalizer-combiner-divrem-insertpt-crash.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizer-combiner-icmp-to-true-false-known-bits.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizer-combiner-load-and-mask.mir
|
[GlobalISel] Add a combine for and(load , mask) -> zextload
|
2021-09-16 10:42:46 +02:00 |
|
prelegalizer-combiner-load-or-pattern-align.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizer-combiner-load-or-pattern.mir
|
[GlobalISel] Fix load-or combine moving loads across potential aliasing stores.
|
2021-07-19 10:23:23 -07:00 |
|
prelegalizer-combiner-mulo-zero.mir
|
[GlobalISel] Combine: (G_*MULO x, 0) -> 0 + no carry out
|
2022-02-03 14:23:58 -08:00 |
|
prelegalizer-combiner-narrow-binop-feeding-add.mir
|
[GlobalISel] Narrow binops feeding into G_AND with a mask
|
2021-08-13 18:31:13 -07:00 |
|
prelegalizercombiner-ashr-shl-to-sext-inreg.mir
|
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
|
2020-08-18 10:42:15 -07:00 |
|
prelegalizercombiner-binop-same-val.mir
|
…
|
|
|
prelegalizercombiner-br.mir
|
[GlobalISel] Check if branches use the same MBB in matchOptBrCondByInvertingCond
|
2021-02-02 15:38:48 -08:00 |
|
prelegalizercombiner-bzero.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-concat-vectors.mir
|
[GISel]: Few InsertVecElt combines
|
2020-10-28 12:27:07 -07:00 |
|
prelegalizercombiner-copy-prop-disabled.mir
|
…
|
|
|
prelegalizercombiner-extending-loads-cornercases.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-extending-loads-s1.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-extending-loads.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-funnel-shifts-to-rotates.mir
|
[AArch64][GlobalISel] Combine funnel shifts to rotates.
|
2021-03-30 11:00:36 -07:00 |
|
prelegalizercombiner-hoist-same-hands.mir
|
[GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
|
2020-08-11 10:40:06 -07:00 |
|
prelegalizercombiner-icmp-redundant-trunc.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-invert-cmp.mir
|
[GlobalISel] Extend not_cmp_fold to work on conditional expressions
|
2020-09-07 09:31:08 +01:00 |
|
prelegalizercombiner-not-really-equiv-insts.mir
|
[GlobalISel] Don't combine instructions which are fed by memory instructions using different size
|
2022-02-04 15:00:47 -08:00 |
|
prelegalizercombiner-prop-extends-phi.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-ptradd-chain.mir
|
[AArch64][GlobalISel] Relax oneuse restriction for PTR_ADD chain combining to check addressing legality.
|
2021-08-10 16:41:18 -07:00 |
|
prelegalizercombiner-select.mir
|
Recommit "[GlobalISel] Walk through hints in getDefIgnoringCopies et al"
|
2021-01-28 14:43:00 -08:00 |
|
prelegalizercombiner-sextload-from-sextinreg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizercombiner-shuffle-vector.mir
|
…
|
|
|
prelegalizercombiner-simplify-add.mir
|
…
|
|
|
prelegalizercombiner-trivial-arith.mir
|
[AArch64][GlobalISel] Fix combiner assertion in matchConstantOp().
|
2021-10-11 15:55:13 -07:00 |
|
prelegalizercombiner-undef.mir
|
…
|
|
|
prelegalizercombiner-xor-of-and-with-same-reg.mir
|
[GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y)
|
2020-09-28 10:08:14 -07:00 |
|
preselect-process-phis.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
rbs-matrixindex-regclass-crash.mir
|
[AArch64][GlobalISel] Fix an crash in RBS due to a new regclass being added.
|
2021-10-29 11:47:00 -07:00 |
|
reg-bank-128bit.mir
|
…
|
|
|
regbank-assert-align.mir
|
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
|
2022-01-24 09:26:52 -05:00 |
|
regbank-assert-sext.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbank-assert-zext.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbank-ceil.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbank-dup.mir
|
[AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.
|
2021-02-21 21:17:29 -08:00 |
|
regbank-extract-vector-elt.mir
|
[AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b.
|
2020-09-17 11:50:33 -07:00 |
|
regbank-extract.mir
|
AArch64: support i128 cmpxchg in GlobalISel.
|
2021-05-14 10:41:38 +01:00 |
|
regbank-fcmp.mir
|
[AArch64][GlobalISel] Fix regbankselect for G_FCMP with vector destinations
|
2021-04-21 18:11:30 -07:00 |
|
regbank-fma.mir
|
…
|
|
|
regbank-fmaximum.mir
|
[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
|
2021-12-09 12:52:32 -08:00 |
|
regbank-fminimum.mir
|
[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
|
2021-12-09 12:52:32 -08:00 |
|
regbank-fp-use-def.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbank-inlineasm.mir
|
[AArch64][SME] Add load and store instructions
|
2021-07-16 10:11:10 +00:00 |
|
regbank-insert-vector-elt.mir
|
…
|
|
|
regbank-intrinsic-round.mir
|
…
|
|
|
regbank-intrinsic-trunc.mir
|
…
|
|
|
regbank-intrinsic.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbank-llround.mir
|
[AArch64][GlobalISel] Add regbankselect support for G_LLROUND
|
2021-08-23 10:32:20 -07:00 |
|
regbank-lround.mir
|
[AArch64][GlobalISel] Add regbankselect support for G_LROUND
|
2021-08-20 14:31:14 -07:00 |
|
regbank-maxnum.mir
|
[AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
|
2021-08-18 13:32:19 -07:00 |
|
regbank-minnum.mir
|
[AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
|
2021-08-18 13:32:19 -07:00 |
|
regbank-nearbyint.mir
|
…
|
|
|
regbank-select.mir
|
…
|
|
|
regbank-shift-imm-64.mir
|
…
|
|
|
regbank-trunc-s128.mir
|
…
|
|
|
regbankselect-build-vector.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-dbg-value.mir
|
…
|
|
|
regbankselect-default.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-reductions.mir
|
[AArch64][GlobalISel] Regbankselect reductions to use FPR bank for scalars.
|
2020-10-16 10:42:15 -07:00 |
|
regbankselect-reg_sequence.mir
|
…
|
|
|
regbankselect-unmerge-vec.mir
|
…
|
|
|
ret-1x-vec.ll
|
GlobalISel: Merge and cleanup more AMDGPU call lowering code
|
2021-03-02 17:31:13 -05:00 |
|
ret-vec-promote.ll
|
Fix the default alignment of i1 vectors.
|
2021-07-31 14:09:59 -07:00 |
|
retry-artifact-combine.mir
|
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
|
2021-08-24 11:09:56 +02:00 |
|
select-abs.mir
|
[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
|
2021-04-21 18:10:40 -07:00 |
|
select-add-low.mir
|
[Aarch64] Correct register class for pseudo instructions
|
2021-09-09 14:31:49 -04:00 |
|
select-arith-extended-reg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-arith-shifted-reg.mir
|
…
|
|
|
select-atomic-load-store.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-atomicrmw.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-binop.mir
|
AArch64 GIsel: legalize lshr operands, even if it is poison
|
2021-11-30 15:28:35 -05:00 |
|
select-bitcast-bigendian.mir
|
…
|
|
|
select-bitcast.mir
|
…
|
|
|
select-bitfield-insert.ll
|
[AArch64][GISel] and+or+shl => bfi
|
2021-06-17 12:52:59 -07:00 |
|
select-bitreverse.mir
|
[AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them
|
2021-06-10 10:33:52 -07:00 |
|
select-blockaddress.mir
|
[GlobalISel] Clear unreachable blocks' contents after selection.
|
2021-10-05 23:06:22 -07:00 |
|
select-br.mir
|
…
|
|
|
select-brcond-of-binop.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-bswap.mir
|
…
|
|
|
select-build-vector.mir
|
[AArch64][GlobalISel] Optimize G_BUILD_VECTOR of undef + 1 elt -> SUBREG_TO_REG
|
2021-08-26 11:45:11 -07:00 |
|
select-cbz.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-ceil.mir
|
…
|
|
|
select-cmp.mir
|
[AArch64][GlobalISel] Fold 64-bit cmps with 64-bit adds
|
2021-10-21 13:51:44 -07:00 |
|
select-cmpxchg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-concat-vectors.mir
|
[AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal
|
2021-08-05 09:40:46 -07:00 |
|
select-const-pool.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-const-vector.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-constant.mir
|
[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.
|
2020-09-09 13:08:16 -07:00 |
|
select-ctlz.mir
|
[AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
|
2021-03-23 12:49:10 -07:00 |
|
select-ctpop.mir
|
[AArch64][GlobalISel] Mark G_CTPOP as legal for v16s8 and v8s8
|
2021-04-13 11:03:39 -07:00 |
|
select-dbg-value.mir
|
[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.
|
2021-12-05 15:55:59 -05:00 |
|
select-dup.mir
|
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
|
2021-03-08 13:01:10 -08:00 |
|
select-ext.mir
|
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.
|
2021-05-11 12:38:53 -07:00 |
|
select-extload.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-extract-vector-elt-with-extend.mir
|
[AArch64][GlobalISel] Fix crash in the extend(extract_vector_elt) optimization.
|
2021-09-23 23:07:16 -07:00 |
|
select-extract-vector-elt.mir
|
[AArch64] Rename CPY to DUP. NFC
|
2022-01-05 20:02:39 +00:00 |
|
select-extract.mir
|
[AArch64] Rename CPY to DUP. NFC
|
2022-01-05 20:02:39 +00:00 |
|
select-fabs.mir
|
…
|
|
|
select-faddp.mir
|
[AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD.
|
2020-11-03 17:25:14 -08:00 |
|
select-fcmp.mir
|
AArch64: fix regression introduced by fcmp immediate selection.
|
2021-01-15 22:53:25 -08:00 |
|
select-floor.mir
|
…
|
|
|
select-fma.mir
|
…
|
|
|
select-fmul-indexed.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-fp-casts.mir
|
AArch64: support mixed-size fp <-> int conversions in GlobalISel.
|
2021-04-22 15:03:17 +01:00 |
|
select-fp16-fconstant.mir
|
[AArch64][GlobalISel] Select full-fp16 s16 G_FCONSTANT as a constant pool load
|
2021-09-10 19:36:34 -07:00 |
|
select-frameaddr.ll
|
…
|
|
|
select-frint-nofp16.mir
|
[AArch64] Rename CPY to DUP. NFC
|
2022-01-05 20:02:39 +00:00 |
|
select-frint.mir
|
…
|
|
|
select-gv-cmodel-large.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-gv-cmodel-tiny.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-gv-with-offset.mir
|
[Aarch64] Correct register class for pseudo instructions
|
2021-09-09 14:31:49 -04:00 |
|
select-hint.mir
|
[GlobalISel] Add G_ASSERT_SEXT
|
2021-02-17 13:10:34 -08:00 |
|
select-imm.mir
|
[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
|
2021-03-02 12:55:51 -08:00 |
|
select-implicit-def.mir
|
…
|
|
|
select-insert-extract.mir
|
…
|
|
|
select-insert-vector-elt.mir
|
Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar.""
|
2020-09-28 13:44:51 -07:00 |
|
select-int-ext.mir
|
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
|
2021-05-18 10:00:00 -07:00 |
|
select-int-ptr-casts.mir
|
[AArch64][GlobalISel] Legalize + select v2p0 -> v264 G_PTRTOINT
|
2021-08-24 11:02:01 -07:00 |
|
select-intrinsic-aarch64-hint.mir
|
…
|
|
|
select-intrinsic-aarch64-sdiv.mir
|
…
|
|
|
select-intrinsic-crypto-aesmc.mir
|
…
|
|
|
select-intrinsic-round.mir
|
…
|
|
|
select-intrinsic-trunc.mir
|
…
|
|
|
select-intrinsic-uaddlv.mir
|
[AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv
|
2021-04-19 10:47:49 -07:00 |
|
select-jump-table-brjt-constrain.mir
|
[Aarch64] Correct register class for pseudo instructions
|
2021-09-09 14:31:49 -04:00 |
|
select-jump-table-brjt.mir
|
[Aarch64] Correct register class for pseudo instructions
|
2021-09-09 14:31:49 -04:00 |
|
select-ld2.mir
|
[AArch64][GlobalISel] Select @llvm.aarch64.neon.ld2.*
|
2021-08-23 17:15:53 -07:00 |
|
select-ld4.mir
|
[AArch64][GlobalISel] Select @llvm.aarch64.neon.ld4.*
|
2021-08-24 09:03:49 -07:00 |
|
select-ldaxr-intrin.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-ldxr-intrin.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-load-store-vector-of-ptr.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-load.mir
|
[AArch64][GlobalISel] Handle any-extending FPR loads in manual selection code.
|
2021-09-01 10:19:22 -07:00 |
|
select-logical-imm.mir
|
…
|
|
|
select-logical-shifted-reg.mir
|
…
|
|
|
select-mul.mir
|
[AArch64][GlobalISel] Add selection tests for vector G_UMULH/G_SMULH.
|
2021-09-29 02:55:08 -07:00 |
|
select-muladd.mir
|
…
|
|
|
select-nearbyint.mir
|
…
|
|
|
select-neon-vcvtfxu2fp.mir
|
…
|
|
|
select-neon-vector-fcmp.mir
|
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
|
2021-05-10 15:40:06 -07:00 |
|
select-phi.mir
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…
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|
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select-pr32733.mir
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…
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|
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select-property.mir
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…
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|
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select-ptr-add.mir
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[AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB.
|
2020-11-11 22:46:53 -08:00 |
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select-reduce-add.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-reduce-fadd.mir
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[AArch64][GlobalISel] Add selection support for v2s32 and v2s64 reductions for FADD/ADD.
|
2020-10-16 11:41:57 -07:00 |
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select-redundant-zext-of-load.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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select-redundant-zext.mir
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[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
|
2021-05-18 10:00:00 -07:00 |
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select-returnaddr.ll
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[AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET
|
2020-09-24 18:04:37 +01:00 |
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select-returnaddress-liveins.mir
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[AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET
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2020-09-24 18:04:37 +01:00 |
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select-rev.mir
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…
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|
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select-rotate.mir
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[AArch64][GlobalISel] Support for folding G_ROTR as shifted operands.
|
2021-09-02 21:37:24 -07:00 |
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select-saddo.mir
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Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
|
2021-01-22 17:29:54 -08:00 |
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select-sbfx.mir
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[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
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2021-04-29 21:54:19 -04:00 |
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select-scalar-merge.mir
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…
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|
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select-scalar-shift-imm.mir
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AArch64 GIsel: legalize lshr operands, even if it is poison
|
2021-11-30 15:28:35 -05:00 |
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select-select.mir
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[AArch64][GlobalISel] Fold selects fed by G_PTR_ADD
|
2021-02-10 00:03:13 -08:00 |
|
select-sextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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select-shuffle-vector.mir
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…
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|
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select-shufflevec-undef-mask-elt.mir
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…
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|
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select-sqrt.mir
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…
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|
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select-ssubo.mir
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Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
|
2021-01-22 17:29:54 -08:00 |
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select-st2.mir
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[AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics
|
2021-07-20 13:23:46 -07:00 |
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select-static.mir
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[Aarch64] Correct register class for pseudo instructions
|
2021-09-09 14:31:49 -04:00 |
|
select-stlxr-intrin.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-store-truncating-float.mir
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[AArch64][GlobalISel] Fix incorrect handling of fp truncating stores.
|
2021-08-24 16:07:00 -07:00 |
|
select-store.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-stx.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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select-trap.mir
|
…
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|
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select-trn.mir
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…
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select-trunc.mir
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…
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|
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select-truncstore-atomic.mir
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[AArch64][GlobalISel] Fix atomic truncating stores from generating invalid copies.
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2021-11-09 20:47:50 -08:00 |
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select-uaddo.mir
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[AArch64][GlobalISel] Select arith extended add/sub in manual selection code
|
2020-11-11 09:26:03 -08:00 |
|
select-ubfx.mir
|
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
|
2021-04-29 21:54:19 -04:00 |
|
select-unmerge.mir
|
[AArch64] Rename CPY to DUP. NFC
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2022-01-05 20:02:39 +00:00 |
|
select-unreachable-blocks.mir
|
[GlobalISel] Clear unreachable blocks' contents after selection.
|
2021-10-05 23:06:22 -07:00 |
|
select-usubo.mir
|
Recommit "[AArch64][GlobalISel] Make G_USUBO legal and select it."
|
2021-01-22 17:29:54 -08:00 |
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select-uzp.mir
|
…
|
|
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select-vector-icmp.mir
|
…
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|
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select-vector-shift.mir
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[AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR.
|
2021-04-09 10:41:41 -07:00 |
|
select-with-no-legality-check.mir
|
[AArch64][GlobalISel] Fix incorrect handling of fp truncating stores.
|
2021-08-24 16:07:00 -07:00 |
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select-xor.mir
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[AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR at -O0.
|
2020-09-10 15:01:26 -07:00 |
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select-zext-as-copy.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-zextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
select-zip.mir
|
…
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|
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select.mir
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[Aarch64] Correct register class for pseudo instructions
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2021-09-09 14:31:49 -04:00 |
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sext-inreg-ldrow-16b.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
speculative-hardening-brcond.mir
|
[AArch64][GlobalISel] Refactor G_BRCOND selection
|
2020-12-07 17:24:23 -08:00 |
|
store-addressing-modes.mir
|
AArch64/GlobalISel: Update tests to use correct memory types
|
2021-07-16 11:41:32 -04:00 |
|
store-merging.ll
|
[GlobalISel] Add a store-merging optimization pass and enable for AArch64.
|
2021-11-15 21:10:39 -08:00 |
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store-merging.mir
|
[GlobalISel] Add a store-merging optimization pass and enable for AArch64.
|
2021-11-15 21:10:39 -08:00 |
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store-wro-addressing-modes.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
subreg-copy.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
swifterror.ll
|
[AArch64] Make -mcpu=generic schedule for an in-order core
|
2021-10-09 15:58:31 +01:00 |
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swiftself.ll
|
OpaquePtr: Update more tests to use typed sret
|
2020-11-20 20:08:43 -05:00 |
|
tail-call-no-save-fp-lr.ll
|
…
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|
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tbnz-slt.mir
|
[AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z
|
2020-12-01 15:45:14 -08:00 |
|
tbz-sgt.mir
|
[AArch64][GlobalISel] Select negative arithmetic immediates in manual selector
|
2020-11-11 09:20:05 -08:00 |
|
translate-constant-dag.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
translate-gep.ll
|
…
|
|
|
translate-ret.ll
|
AArch64: support i128 (& larger) returns in GlobalISel
|
2021-07-26 14:16:35 +01:00 |
|
uaddo-8-16-bits.mir
|
[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.
|
2021-12-05 15:55:59 -05:00 |
|
ubsantrap.ll
|
AArch64: use correct operand for ubsantrap immediate.
|
2020-12-09 10:17:16 +00:00 |
|
unknown-intrinsic.ll
|
…
|
|
|
unwind-inline-asm.ll
|
Support unwinding from inline assembly
|
2021-05-13 19:13:03 +01:00 |
|
v8.4-atomic-128.ll
|
AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards
|
2021-09-20 09:50:11 +01:00 |
|
varargs-ios-translator.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
vastart.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
vec-s16-param.ll
|
[AArch64][GlobalISel] Support lowering <1 x i8> arguments.
|
2021-02-22 13:58:44 -08:00 |
|
widen-narrow-tbz-tbnz.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
xro-addressing-mode-constant.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
