39 lines
1.1 KiB
LLVM
39 lines
1.1 KiB
LLVM
; RUN: llc -march=hexagon -O0 < %s
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; This is a regression test which makes sure that the offset check
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; is available for STRiw_indexed instruction. This is required
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; by 'Hexagon Expand Predicate Spill Code' pass.
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define i32 @f0(i32 %a0, i32 %a1) #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32, align 4
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%v2 = alloca i32, align 4
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store i32 %a0, i32* %v1, align 4
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store i32 %a1, i32* %v2, align 4
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%v3 = load i32, i32* %v1, align 4
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%v4 = load i32, i32* %v2, align 4
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%v5 = icmp sgt i32 %v3, %v4
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br i1 %v5, label %b1, label %b2
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b1: ; preds = %b0
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%v6 = load i32, i32* %v1, align 4
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%v7 = load i32, i32* %v2, align 4
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%v8 = add nsw i32 %v6, %v7
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store i32 %v8, i32* %v0
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br label %b3
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b2: ; preds = %b0
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%v9 = load i32, i32* %v1, align 4
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%v10 = load i32, i32* %v2, align 4
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%v11 = sub nsw i32 %v9, %v10
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store i32 %v11, i32* %v0
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br label %b3
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b3: ; preds = %b2, %b1
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%v12 = load i32, i32* %v0
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ret i32 %v12
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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