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llvm-project/llvm/test/CodeGen/RISCV
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Zakk Chen 093ecccdab [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics. 
The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D119686
 		2022-02-17 02:21:39 -08:00
..
GlobalISel [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
intrinsics
…
rvv [RISCV] Add the passthru operand for vadc/vsbc/vmerge/vfmerge IR intrinsics. 2022-02-17 02:21:39 -08:00
MachineSink-implicit-x0.mir Fix minor deficiency in machine-sink. 2021-11-12 08:01:13 +01:00
add-before-shl.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
add-imm.ll [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns. 2021-08-18 11:07:11 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll [test][DAGCombine] Add more tests for carry diamond. NFC 2022-01-27 00:25:26 +01:00
addimm-mulimm.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
addrspacecast.ll [RISCV] Assume no-op addrspacecasts by default 2020-12-18 21:03:37 +00:00
aext-to-sext.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
align-loops.ll [CodeGen] Add -align-loops 2021-08-04 12:45:18 -07:00
align.ll
…
alloca.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
alu8.ll [RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16), (XLen-16) + C) optimization. 2022-01-09 23:37:10 -08:00
alu16.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
alu32.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
alu64.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
analyze-branch.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
and.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
arith-with-overflow.ll
…
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
atomic-fence.ll
…
atomic-load-store.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
atomic-rmw.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
atomic-signext.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
attributes.ll [RISCV] Recover the implication between Zve* extensions and the V extension. 2022-02-14 15:52:07 +08:00
blockaddress.ll
…
branch-relaxation.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
branch.ll [RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0) 2021-03-15 11:32:43 -07:00
bswap-bitreverse.ll [RISCV] Custom legalize BITREVERSE with Zbkb. 2022-01-28 23:11:12 -08:00
byval.ll [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
callee-saved-fpr32s.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
callee-saved-fpr64s.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
callee-saved-gprs.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-half.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
calling-conv-ilp32-ilp32f-common.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-ilp32.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-ilp32d.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-ilp32f-ilp32d-common.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-lp64-lp64f-common.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-lp64-lp64f-lp64d-common.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
calling-conv-lp64.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
calling-conv-rv32f-ilp32.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
calling-conv-sext-zext.ll [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
calling-conv-vector-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
calls.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
compress-float.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
compress-inline-asm.ll
…
compress.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
copy-frameindex.mir [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
copysign-casts.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
ctlz-cttz-ctpop.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
disable-tail-calls.ll
…
disjoint.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
div-by-constant.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
div-pow2.ll [RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT 2022-01-11 15:54:35 +08:00
div.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
double-arith-strict.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
double-arith.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
double-bitmanip-dagcombines.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
double-br-fcmp.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
double-calling-conv.ll [RISCV] Split f64 undef into two i32 undefs 2022-02-08 13:42:15 +08:00
double-convert-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
double-convert.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
double-fcmp-strict.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
double-fcmp.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
double-frem.ll [RISCV] Promote f16 frem with Zfh. 2021-11-10 17:35:07 -08:00
double-imm.ll [RISCV] Use constant pool for large integers 2021-12-31 14:48:48 +08:00
double-intrinsics-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
double-intrinsics.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
double-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
double-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
double-previous-failure.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
double-round-conv-sat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
double-round-conv.ll [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn) 2022-01-11 09:05:57 -08:00
double-select-fcmp.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
double-stack-spill-restore.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
dwarf-eh.ll
…
elf-preemption.ll [RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local 2021-05-11 11:29:45 -07:00
exception-pointer-register.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
fastcc-float.ll [RISCV] Fix a crash when lowering split float arguments 2021-07-22 09:55:26 +01:00
fastcc-int.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
fixups-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
fixups-relax-diff.ll test: clean up some of the RISCV tests (NFC) 2021-06-17 09:51:09 -07:00
float-arith-strict.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
float-arith.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
float-bit-preserving-dagcombines.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
float-bitmanip-dagcombines.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
float-br-fcmp.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
float-convert-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
float-convert.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
float-fcmp-strict.ll [RISCV] Add strictfp support for compares. 2022-01-11 20:01:41 -08:00
float-fcmp.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
float-frem.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
float-imm.ll
…
float-intrinsics-strict.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
float-intrinsics.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
float-isnan.ll [RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal. 2020-12-10 09:15:52 -08:00
float-mem.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
float-round-conv-sat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
float-round-conv.ll [RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn) 2022-01-11 09:05:57 -08:00
float-select-fcmp.ll [RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC 2022-01-10 09:08:29 -08:00
flt-rounds.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
fold-addi-loadstore.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
fp-imm.ll [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00
fp16-promote.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
fp128.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
fpclamptosat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
fpclamptosat_vec.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
fpenv.ll [RISCV] Custom lowering of SET_ROUNDING 2021-04-22 15:04:55 +07:00
frame-info.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
frame.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
frameaddr-returnaddr.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
frm-dependency.ll [RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode. 2021-12-14 10:17:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
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ghccc-rv32.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
ghccc-rv64.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
half-arith-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-arith.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
half-bitmanip-dagcombines.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-br-fcmp.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
half-convert-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-convert.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
half-fcmp-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-fcmp.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-frem.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-imm.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-intrinsics.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
half-isnan.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-mem.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-round-conv-sat.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
half-round-conv.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
half-select-fcmp.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
hoist-global-addr-base.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
i32-icmp.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
imm-cse.ll
…
imm.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
indirectbr.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
init-array.ll
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inline-asm-S-constraint.ll [RISCV] Support machine constraint "S" 2021-07-13 09:30:09 -07:00
inline-asm-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
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inline-asm-f-abi-names.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
inline-asm-f-constraint-f.ll [RISCV] Honor the VT when converting float point register names to register class for inline assembly. 2022-01-14 09:04:00 -08:00
inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll [RISCV] Don't allow vector types to be used with inline asm 'r' constraint 2021-12-23 20:32:36 -06:00
inline-asm-zfh-constraint-f.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
inline-asm.ll [RISCV] Don't advertise i32->i64 zextload as free for RV64. 2022-01-06 08:13:42 -08:00
interrupt-attr-args-error.ll
…
interrupt-attr-callee.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
interrupt-attr-ret-error.ll
…
interrupt-attr.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
jumptable.ll [RISCV] Generate 32 bits jumptable entries when code model is small 2022-01-11 18:20:37 +08:00
large-stack.ll [RISCV] Fix incomplete asm statement parsing 2022-01-19 21:56:21 +00:00
legalize-fneg.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
lit.local.cfg
…
live-sp.mir [RISCV] Fix invalid kill on callee save 2021-11-02 11:56:54 +00:00
lsr-legaladdimm.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
machine-outliner-patchable.ll [MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL 2021-12-13 13:24:29 -08:00
machineoutliner-jumptable.mir [RISCV] Fix Machine Outliner jump table handling. 2021-09-09 07:32:30 +02:00
machineoutliner.mir
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mattr-invalid-combination.ll
…
mem.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
mem64.ll [RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:28:11 -08:00
mir-target-flags.ll [TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm 2020-12-05 14:54:37 -08:00
module-target-abi.ll
…
module-target-abi2.ll
…
mul.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
musttail-call.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
neg-abs.ll [RISCV][NFC] Increase test coverage of Zbt extension 2021-01-18 17:30:35 +00:00
nomerge.ll
…
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll [DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience 2021-12-23 10:48:28 +05:30
out-of-reach-emergency-slot.mir [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
overflow-intrinsic-optimizations.ll [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() 2021-08-31 11:23:56 -07:00
patchable-function-entry.ll Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases" 2021-05-29 15:11:37 +01:00
pic-models.ll
…
pr40333.ll
…
pr51206.ll [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
prefetch.ll
…
readcyclecounter.ll
…
rem.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
remat.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
reserved-reg-errors.ll
…
reserved-regs.ll
…
rotl-rotr.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
rv32e.ll
…
rv32i-rv64i-float-double.ll [NFC][llvm] Inclusive language: reword uses of sanity test and check 2021-11-25 07:21:42 -05:00
rv32i-rv64i-half.ll [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32 2022-01-29 00:01:00 +08:00
rv32zba.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
rv32zbb-intrinsic.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
rv32zbb-zbp-zbkb.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zbb.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
rv32zbc-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zbc-zbkc-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zbe-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv32zbf-intrinsic.ll [RISCV] Add bfp and bfpw intrinsic in zbf extension 2022-01-13 02:53:00 +00:00
rv32zbkb-intrinsic.ll [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV. 2022-01-30 12:41:09 -08:00
rv32zbkx-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zbp-intrinsic.ll [RISCV] Add isel patterns for grevi, shfli, and unshfli to brev8/zip/unzip instructions. 2022-01-20 20:43:52 -08:00
rv32zbp-zbkb.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zbp.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zbr.ll [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
rv32zbs.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
rv32zbt-intrinsic.ll [RISCV] Add intrinsic for Zbt extension 2022-01-20 08:27:05 +00:00
rv32zbt.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
rv32zknd-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zkne-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zknh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zksed-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv32zksh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64-large-stack.ll [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants. 2021-07-20 09:22:06 -07:00
rv64d-double-convert-strict.ll [RISCV] Support strict FP conversion operations. 2021-12-23 09:40:58 -06:00
rv64d-double-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64f-float-convert-strict.ll [RISCV] Support strict FP conversion operations. 2021-12-23 09:40:58 -06:00
rv64f-float-convert.ll [RISCV] Custom lower (i32 (fptoui/fptosi X)). 2021-07-24 10:50:43 -07:00
rv64i-complex-float.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
rv64i-demanded-bits.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64i-double-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-exhaustive-w-insts.ll [RISCV] Remove exclusions for zext.h/zext.w from our (and (srl X, C1), C2) selection code. 2022-02-04 17:10:48 -08:00
rv64i-single-softfloat.ll [RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC 2021-11-11 10:56:27 -08:00
rv64i-tricky-shifts.ll
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rv64i-w-insts-legalization.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
rv64m-exhaustive-w-insts.ll [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used. 2021-08-18 10:22:00 -07:00
rv64m-w-insts-legalization.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
rv64zba.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
rv64zbb-intrinsic.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
rv64zbb-zbp-zbkb.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbb.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
rv64zbc-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbc-zbkc-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbe-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbf-intrinsic.ll [RISCV] Add RISCVISD::BFPW to ComputeNumSignBitsForTargetNode. 2022-01-15 15:23:49 -08:00
rv64zbkb-intrinsic.ll [RISCV] Custom lower brev8 intrinsic to RISCVISD::GREV. 2022-01-30 12:41:09 -08:00
rv64zbkx-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbp-intrinsic.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zbp-zbkb.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbp.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zbr.ll [RISCV] Add IR intrinsic for Zbr extension 2021-04-02 10:58:45 -07:00
rv64zbs.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
rv64zbt-intrinsic.ll [RISCV] Add intrinsic for Zbt extension 2022-01-20 08:27:05 +00:00
rv64zbt.ll [RISCV] Remove experimental-b extension that includes all Zb* extensions 2021-10-07 20:47:17 -07:00
rv64zfh-half-convert-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zfh-half-convert.ll Revert "[RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)." 2022-02-05 12:51:01 -08:00
rv64zfh-half-intrinsics-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zfh-half-intrinsics.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
rv64zknd-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zknd-zkne-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zkne-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zknh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zksed-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
rv64zksh-intrinsic.ll [RISCV][CodeGen] Implement IR Intrinsic support for K extension 2022-01-27 15:53:35 +08:00
sadd_sat.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
sadd_sat_plus.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
saverestore.ll [RISCV] Don't emit save-restore call if function is a interrupt handler 2021-04-16 12:54:47 +08:00
scalable-vector-struct.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-bare.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
select-binop-identity.ll [RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y)) 2021-08-10 09:02:56 -07:00
select-cc.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
select-const.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
select-constant-xor.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
select-optimize-multiple.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
select-optimize-multiple.mir [RISCV] Reorder the vector register allocation order. 2021-10-19 09:30:13 +08:00
select-or.ll Recommit "[RISCV] Legalize select when Zbt extension available" 2021-01-21 12:07:44 -08:00
selectcc-to-shiftand.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
setcc-logic.ll [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. 2021-08-18 10:44:25 -07:00
sext-zext-trunc.ll [RISCV] Use shift for zero extension when Zbb and Zbp are not enabled 2022-01-11 02:37:03 +00:00
sextw-removal.ll [RISCV] Add FMV_X_W and FMV_X_H to RISCVSExtWRemoval. 2022-02-03 09:40:47 -08:00
shadowcallstack.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
shift-and.ll [RISCV] Add another isel optimization for (and (shl x, c2), c1) 2021-09-23 14:18:07 -07:00
shift-masked-shamt.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
shifts.ll [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS. 2022-02-16 09:22:11 -08:00
shlimm-addimm.ll [RISCV][test] Add tests of (add (shl r, c0), c1) 2021-10-14 14:53:03 +00:00
shrinkwrap.ll Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
sink-icmp.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
spill-fpr-scalar.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
split-offsets.ll [RISCV] Add an MIR pass to replace redundant sext.w instructions with copies. 2022-01-06 08:23:42 -08:00
split-sp-adjust.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
srem-lkk.ll [RISCV] Use constant pool for large integers 2021-12-31 14:48:48 +08:00
srem-seteq-illegal-types.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
srem-vector-lkk.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
ssub_sat.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
ssub_sat_plus.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
stack-realignment-with-variable-sized-objects.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
stack-realignment.ll [RISCV] Reverse the order of loading/storing callee-saved registers. 2021-11-22 23:02:11 +08:00
stack-slot-size.ll [RISCV] Generate pseudo instruction li 2021-11-22 14:01:37 +08:00
stack-store-check.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
subtarget-features-std-ext.ll
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tail-calls.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
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tls-models.ll [RISCV][NFC] Regenerate RISCV CodeGen tests 2020-12-09 19:42:49 +00:00
uadd_sat.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
uadd_sat_plus.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
umulo-128-legalisation-lowering.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
unfold-masked-merge-scalar-variablemask.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
unroll-loop-cse.ll Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
urem-lkk.ll [RISCV] Use constant pool for large integers 2021-12-31 14:48:48 +08:00
urem-seteq-illegal-types.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
urem-vector-lkk.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
usub_sat.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
usub_sat_plus.ll [RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental 2022-01-12 19:33:44 +00:00
vararg.ll [RISCV] Use constant pool for large integers 2021-12-31 14:48:48 +08:00
vec3-setcc-crash.ll [RISCV] Remove experimental prefix from rvv-related extensions. 2022-01-22 20:18:40 -08:00
vector-abi.ll CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
verify-instr.mir
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wide-mem.ll
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xaluo.ll [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
zext-with-load-is-free.ll [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
zfh-half-intrinsics-strict.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
zfh-half-intrinsics.ll [RISCV] update zfh and zfhmin extention to v1.0 2022-01-15 09:21:24 +08:00
zfh-imm.ll [RISCV] Optimize lowering of floating-point -0.0 2022-01-20 11:46:28 +00:00