225 lines
5.8 KiB
LLVM
225 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+cmov | FileCheck %s --check-prefix=X64
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;
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; PR48768 - 'and' clears the overflow flag, so we don't need a separate 'test'.
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;
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define i8 @and_i8_ri(i8 zeroext %0, i8 zeroext %1) {
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; X86-LABEL: and_i8_ri:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: andb $-17, %cl
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; X86-NEXT: je .LBB0_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB0_2:
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i8_ri:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andb $-17, %al
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; X64-NEXT: movzbl %al, %eax
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; X64-NEXT: cmovel %edi, %eax
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%3 = and i8 %0, -17
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%4 = icmp eq i8 %3, 0
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%5 = select i1 %4, i8 %0, i8 %3
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ret i8 %5
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}
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define i8 @and_i8_rr(i8 zeroext %0, i8 zeroext %1) {
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; X86-LABEL: and_i8_rr:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-NEXT: andb %al, %cl
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; X86-NEXT: je .LBB1_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB1_2:
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i8_rr:
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; X64: # %bb.0:
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: cmovel %edi, %eax
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%3 = and i8 %1, %0
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%4 = icmp eq i8 %3, 0
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%5 = select i1 %4, i8 %0, i8 %3
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ret i8 %5
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}
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define i16 @and_i16_ri(i16 zeroext %0, i16 zeroext %1) {
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; X86-LABEL: and_i16_ri:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: andl $-17, %ecx
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; X86-NEXT: testw %cx, %cx
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; X86-NEXT: je .LBB2_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB2_2:
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i16_ri:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $-17, %eax
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; X64-NEXT: cmovel %edi, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%3 = and i16 %0, -17
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%4 = icmp eq i16 %3, 0
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%5 = select i1 %4, i16 %0, i16 %3
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ret i16 %5
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}
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define i16 @and_i16_rr(i16 zeroext %0, i16 zeroext %1) {
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; X86-LABEL: and_i16_rr:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: andw %ax, %cx
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; X86-NEXT: je .LBB3_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB3_2:
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i16_rr:
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; X64: # %bb.0:
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: cmovel %edi, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%3 = and i16 %1, %0
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%4 = icmp eq i16 %3, 0
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%5 = select i1 %4, i16 %0, i16 %3
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ret i16 %5
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}
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define i32 @and_i32_ri(i32 %0, i32 %1) {
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; X86-LABEL: and_i32_ri:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: andl $-17, %ecx
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; X86-NEXT: jle .LBB4_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB4_2:
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i32_ri:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $-17, %eax
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; X64-NEXT: cmovlel %edi, %eax
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; X64-NEXT: retq
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%3 = and i32 %0, -17
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%4 = icmp slt i32 %3, 1
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%5 = select i1 %4, i32 %0, i32 %3
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ret i32 %5
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}
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define i32 @and_i32_rr(i32 %0, i32 %1) {
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; X86-LABEL: and_i32_rr:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: andl %eax, %ecx
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; X86-NEXT: jle .LBB5_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB5_2:
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i32_rr:
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; X64: # %bb.0:
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: andl %edi, %eax
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; X64-NEXT: cmovlel %edi, %eax
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; X64-NEXT: retq
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%3 = and i32 %1, %0
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%4 = icmp slt i32 %3, 1
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%5 = select i1 %4, i32 %0, i32 %3
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ret i32 %5
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}
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define i64 @and_i64_ri(i64 %0, i64 %1) nounwind {
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; X86-LABEL: and_i64_ri:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: andl $-17, %ecx
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; X86-NEXT: cmpl $1, %ecx
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; X86-NEXT: movl %edx, %esi
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; X86-NEXT: sbbl $0, %esi
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; X86-NEXT: jl .LBB6_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: .LBB6_2:
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i64_ri:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: andq $-17, %rax
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; X64-NEXT: cmovleq %rdi, %rax
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; X64-NEXT: retq
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%3 = and i64 %0, -17
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%4 = icmp slt i64 %3, 1
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%5 = select i1 %4, i64 %0, i64 %3
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ret i64 %5
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}
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define i64 @and_i64_rr(i64 %0, i64 %1) nounwind {
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; X86-LABEL: and_i64_rr:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: andl %edx, %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: andl %eax, %esi
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; X86-NEXT: cmpl $1, %esi
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; X86-NEXT: movl %ecx, %edi
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; X86-NEXT: sbbl $0, %edi
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; X86-NEXT: jl .LBB7_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %esi, %eax
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; X86-NEXT: movl %ecx, %edx
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; X86-NEXT: .LBB7_2:
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl
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;
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; X64-LABEL: and_i64_rr:
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; X64: # %bb.0:
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; X64-NEXT: movq %rsi, %rax
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; X64-NEXT: andq %rdi, %rax
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; X64-NEXT: cmovleq %rdi, %rax
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; X64-NEXT: retq
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%3 = and i64 %1, %0
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%4 = icmp slt i64 %3, 1
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%5 = select i1 %4, i64 %0, i64 %3
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ret i64 %5
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}
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