71 lines
3.6 KiB
LLVM
71 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -slp-vectorizer -S %s | FileCheck %s
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declare float @memread(float) readonly #0
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declare <4 x float> @vmemread(<4 x float>)
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define <4 x float> @memread_4x(<4 x float>* %a) {
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; CHECK-LABEL: @memread_4x(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
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; CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @vmemread(<4 x float> [[TMP0]])
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; CHECK-NEXT: ret <4 x float> [[TMP1]]
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;
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entry:
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%0 = load <4 x float>, <4 x float>* %a, align 16
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%vecext = extractelement <4 x float> %0, i32 0
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%1 = tail call fast float @memread(float %vecext) #0
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%vecins = insertelement <4 x float> poison, float %1, i32 0
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%vecext.1 = extractelement <4 x float> %0, i32 1
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%2 = tail call fast float @memread(float %vecext.1) #0
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%vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
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%vecext.2 = extractelement <4 x float> %0, i32 2
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%3 = tail call fast float @memread(float %vecext.2) #0
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%vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
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%vecext.3 = extractelement <4 x float> %0, i32 3
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%4 = tail call fast float @memread(float %vecext.3) #0
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%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
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ret <4 x float> %vecins.3
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}
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declare float @memwrite(float) #1
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declare <4 x float> @vmemwrite(<4 x float>)
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define <4 x float> @memwrite_4x(<4 x float>* %a) {
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; CHECK-LABEL: @memwrite_4x(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
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; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) #[[ATTR1:[0-9]+]]
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; CHECK-NEXT: [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
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; CHECK-NEXT: [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) #[[ATTR1]]
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; CHECK-NEXT: [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
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; CHECK-NEXT: [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
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; CHECK-NEXT: [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) #[[ATTR1]]
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; CHECK-NEXT: [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
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; CHECK-NEXT: [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
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; CHECK-NEXT: [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) #[[ATTR1]]
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; CHECK-NEXT: [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
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; CHECK-NEXT: ret <4 x float> [[VECINS_3]]
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;
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entry:
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%0 = load <4 x float>, <4 x float>* %a, align 16
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%vecext = extractelement <4 x float> %0, i32 0
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%1 = tail call fast float @memwrite(float %vecext) #1
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%vecins = insertelement <4 x float> poison, float %1, i32 0
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%vecext.1 = extractelement <4 x float> %0, i32 1
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%2 = tail call fast float @memwrite(float %vecext.1) #1
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%vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
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%vecext.2 = extractelement <4 x float> %0, i32 2
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%3 = tail call fast float @memwrite(float %vecext.2) #1
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%vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
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%vecext.3 = extractelement <4 x float> %0, i32 3
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%4 = tail call fast float @memwrite(float %vecext.3) #1
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%vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
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ret <4 x float> %vecins.3
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}
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attributes #0 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memread(vmemread)" }
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attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memwrite(vmemwrite)" }
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