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llvm-project/llvm/test/MC/Disassembler
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Aleksandar Beserminji f8f00e5065 [mips] Add missing instructions 
Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64.

Differential Revision: https://reviews.llvm.org/D50437

llvm-svn: 340920
 		2018-08-29 11:35:03 +00:00
..
AArch64 [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
AMDGPU AMDGPU: Fix v_dot{4, 8}* instruction encoding 2018-05-15 19:32:47 +00:00
ARC [ARC] Add LImm support for J/JL 2018-04-13 15:10:34 +00:00
ARM [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
Hexagon NFC - Various typo fixes in tests 2018-07-04 13:28:39 +00:00
Lanai
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Mips [mips] Add missing instructions 2018-08-29 11:35:03 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
Sparc
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SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly [WebAssembly] Added default stack-only instruction mode for MC. 2018-08-27 15:45:51 +00:00
X86 [X86] Don't ignore 0x66 prefix on relative jumps in 64-bit mode. Fix opcode selection of relative jumps in 16-bit mode. Treat jno/jo like other jcc instructions. 2018-08-13 22:06:28 +00:00
XCore
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