316 lines
13 KiB
TableGen
316 lines
13 KiB
TableGen
//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Control-flow instructions
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//===----------------------------------------------------------------------===//
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// C's ?: operator for floating-point operands.
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def SelectF32 : SelectWrapper<FP32>;
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def SelectF64 : SelectWrapper<FP64>;
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def SelectF128 : SelectWrapper<FP128>;
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//===----------------------------------------------------------------------===//
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// Move instructions
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//===----------------------------------------------------------------------===//
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// Load zero.
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let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
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def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
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def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
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}
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// Moves between two floating-point registers.
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let neverHasSideEffects = 1 in {
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def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>;
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def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
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def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>;
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}
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// Moves between 64-bit integer and floating-point registers.
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def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>;
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def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>;
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// fcopysign with an FP32 result.
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let isCodeGenOnly = 1 in {
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def CPSDRss : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP32>;
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def CPSDRsd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP32, FP64>;
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}
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// The sign of an FP128 is in the high register.
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def : Pat<(fcopysign FP32:$src1, FP128:$src2),
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(CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
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// fcopysign with an FP64 result.
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let isCodeGenOnly = 1 in
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def CPSDRds : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP32>;
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def CPSDRdd : BinaryRRF<"cpsdr", 0xB372, fcopysign, FP64, FP64>;
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// The sign of an FP128 is in the high register.
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def : Pat<(fcopysign FP64:$src1, FP128:$src2),
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(CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_high))>;
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// fcopysign with an FP128 result. Use "upper" as the high half and leave
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// the low half as-is.
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class CopySign128<RegisterOperand cls, dag upper>
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: Pat<(fcopysign FP128:$src1, cls:$src2),
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(INSERT_SUBREG FP128:$src1, upper, subreg_high)>;
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def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_high),
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FP32:$src2)>;
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def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
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FP64:$src2)>;
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def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
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(EXTRACT_SUBREG FP128:$src2, subreg_high))>;
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//===----------------------------------------------------------------------===//
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// Load instructions
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//===----------------------------------------------------------------------===//
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let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
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defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32>;
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defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64>;
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// These instructions are split after register allocation, so we don't
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// want a custom inserter.
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let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
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def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
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[(set FP128:$dst, (load bdxaddr20only128:$src))]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Store instructions
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//===----------------------------------------------------------------------===//
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let SimpleBDXStore = 1 in {
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defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32>;
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defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64>;
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// These instructions are split after register allocation, so we don't
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// want a custom inserter.
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let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
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def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
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[(store FP128:$src, bdxaddr20only128:$dst)]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Conversion instructions
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//===----------------------------------------------------------------------===//
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// Convert floating-point values to narrower representations, rounding
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// according to the current mode. The destination of LEXBR and LDXBR
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// is a 128-bit value, but only the first register of the pair is used.
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def LEDBR : UnaryRRE<"ledbr", 0xB344, fround, FP32, FP64>;
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def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>;
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def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>;
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def : Pat<(f32 (fround FP128:$src)),
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(EXTRACT_SUBREG (LEXBR FP128:$src), subreg_32bit)>;
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def : Pat<(f64 (fround FP128:$src)),
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(EXTRACT_SUBREG (LDXBR FP128:$src), subreg_high)>;
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// Extend register floating-point values to wider representations.
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def LDEBR : UnaryRRE<"ldebr", 0xB304, fextend, FP64, FP32>;
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def LXEBR : UnaryRRE<"lxebr", 0xB306, fextend, FP128, FP32>;
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def LXDBR : UnaryRRE<"lxdbr", 0xB305, fextend, FP128, FP64>;
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// Extend memory floating-point values to wider representations.
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def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64>;
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def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128>;
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def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128>;
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// Convert a signed integer register value to a floating-point one.
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let Defs = [CC] in {
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def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>;
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def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>;
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def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>;
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def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>;
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def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>;
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def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>;
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}
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// Convert a floating-point register value to a signed integer value,
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// with the second operand (modifier M3) specifying the rounding mode.
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let Defs = [CC] in {
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def CFEBR : UnaryRRF<"cfebr", 0xB398, GR32, FP32>;
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def CFDBR : UnaryRRF<"cfdbr", 0xB399, GR32, FP64>;
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def CFXBR : UnaryRRF<"cfxbr", 0xB39A, GR32, FP128>;
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def CGEBR : UnaryRRF<"cgebr", 0xB3A8, GR64, FP32>;
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def CGDBR : UnaryRRF<"cgdbr", 0xB3A9, GR64, FP64>;
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def CGXBR : UnaryRRF<"cgxbr", 0xB3AA, GR64, FP128>;
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}
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// fp_to_sint always rounds towards zero, which is modifier value 5.
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def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
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def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
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def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
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def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
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def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
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def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
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//===----------------------------------------------------------------------===//
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// Unary arithmetic
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//===----------------------------------------------------------------------===//
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// Negation (Load Complement).
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let Defs = [CC] in {
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def LCEBR : UnaryRRE<"lcebr", 0xB303, fneg, FP32, FP32>;
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def LCDBR : UnaryRRE<"lcdbr", 0xB313, fneg, FP64, FP64>;
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def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;
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}
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// Absolute value (Load Positive).
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let Defs = [CC] in {
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def LPEBR : UnaryRRE<"lpebr", 0xB300, fabs, FP32, FP32>;
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def LPDBR : UnaryRRE<"lpdbr", 0xB310, fabs, FP64, FP64>;
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def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;
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}
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// Negative absolute value (Load Negative).
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let Defs = [CC] in {
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def LNEBR : UnaryRRE<"lnebr", 0xB301, fnabs, FP32, FP32>;
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def LNDBR : UnaryRRE<"lndbr", 0xB311, fnabs, FP64, FP64>;
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def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;
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}
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// Square root.
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def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>;
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def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>;
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def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>;
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def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32>;
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def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64>;
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// Round to an integer, with the second operand (modifier M3) specifying
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// the rounding mode.
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//
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// These forms always check for inexact conditions. z196 added versions
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// that allow this to suppressed (as for fnearbyint), but we don't yet
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// support -march=z196.
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let Defs = [CC] in {
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def FIEBR : UnaryRRF<"fiebr", 0xB357, FP32, FP32>;
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def FIDBR : UnaryRRF<"fidbr", 0xB35F, FP64, FP64>;
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def FIXBR : UnaryRRF<"fixbr", 0xB347, FP128, FP128>;
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}
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// frint rounds according to the current mode (modifier 0) and detects
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// inexact conditions.
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def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
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def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
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def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
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//===----------------------------------------------------------------------===//
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// Binary arithmetic
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//===----------------------------------------------------------------------===//
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// Addition.
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let Defs = [CC] in {
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let isCommutable = 1 in {
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def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>;
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def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>;
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def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>;
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}
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def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load>;
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def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load>;
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}
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// Subtraction.
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let Defs = [CC] in {
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def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>;
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def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>;
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def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>;
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def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load>;
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def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load>;
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}
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// Multiplication.
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let isCommutable = 1 in {
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def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>;
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def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>;
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def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>;
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}
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def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load>;
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def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load>;
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// f64 multiplication of two FP32 registers.
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def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>;
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def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
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(MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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FP32:$src1, subreg_32bit), FP32:$src2)>;
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// f64 multiplication of an FP32 register and an f32 memory.
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def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load>;
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def : Pat<(fmul (f64 (fextend FP32:$src1)),
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(f64 (extloadf32 bdxaddr12only:$addr))),
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(MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_32bit),
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bdxaddr12only:$addr)>;
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// f128 multiplication of two FP64 registers.
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def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>;
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def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
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(MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
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FP64:$src1, subreg_high), FP64:$src2)>;
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// f128 multiplication of an FP64 register and an f64 memory.
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def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load>;
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def : Pat<(fmul (f128 (fextend FP64:$src1)),
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(f128 (extloadf64 bdxaddr12only:$addr))),
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(MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_high),
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bdxaddr12only:$addr)>;
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// Fused multiply-add.
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def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32>;
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def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64>;
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def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load>;
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def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load>;
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// Fused multiply-subtract.
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def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32>;
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def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64>;
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def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load>;
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def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load>;
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// Division.
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def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>;
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def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>;
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def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>;
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def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load>;
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def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load>;
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//===----------------------------------------------------------------------===//
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// Comparisons
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//===----------------------------------------------------------------------===//
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let Defs = [CC] in {
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def CEBR : CompareRRE<"cebr", 0xB309, z_cmp, FP32, FP32>;
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def CDBR : CompareRRE<"cdbr", 0xB319, z_cmp, FP64, FP64>;
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def CXBR : CompareRRE<"cxbr", 0xB349, z_cmp, FP128, FP128>;
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def CEB : CompareRXE<"ceb", 0xED09, z_cmp, FP32, load>;
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def CDB : CompareRXE<"cdb", 0xED19, z_cmp, FP64, load>;
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}
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//===----------------------------------------------------------------------===//
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// Peepholes
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//===----------------------------------------------------------------------===//
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def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
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def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
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def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;
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