18 lines
540 B
LLVM
18 lines
540 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s
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; Check that we generate dual stores in one packet in V4
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; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##500000
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; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}={{ *}}##100000
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; CHECK-NEXT: }
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@Reg = global i32 0, align 4
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define i32 @main() nounwind {
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entry:
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%number= alloca i32, align 4
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store i32 500000, i32* %number, align 4
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%number1= alloca i32, align 4
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store i32 100000, i32* %number1, align 4
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ret i32 0
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}
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