54 lines
2.1 KiB
LLVM
54 lines
2.1 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that we generate an unaligned vector store for a spill when a function
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; has an alloca. Also, make sure the addressing mode for unaligned store does
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; is not a base+offset with a non-zero offset that is not a multiple of 128.
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; CHECK: vmemu(r{{[0-9]+}}+#0)
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%s.0 = type { [5 x [4 x i8]], i32, i32, i32, i32 }
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; Function Attrs: nounwind
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define i32 @f0(i8* nocapture readonly %a0, i8* nocapture %a1, i8* nocapture readonly %a2, i8* nocapture readonly %a3, i32 %a4, i32 %a5, i32 %a6, %s.0* nocapture readonly %a7) #0 {
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b0:
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%v0 = alloca i8, i32 %a4, align 128
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br i1 undef, label %b1, label %b5
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b1: ; preds = %b0
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%v1 = icmp sgt i32 %a5, 2
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br label %b2
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b2: ; preds = %b3, %b2, %b1
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br i1 undef, label %b3, label %b2
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b3: ; preds = %b2
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call void @f1(i8* undef, i8* undef, i8* nonnull %v0, i32 %a4, i32 %a5, %s.0* %a7)
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%v2 = tail call <32 x i32> @llvm.hexagon.V6.vd0.128B() #2
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br i1 %v1, label %b4, label %b2
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b4: ; preds = %b4, %b3
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%v3 = phi <32 x i32> [ %v5, %b4 ], [ undef, %b3 ]
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%v4 = tail call <32 x i32> @llvm.hexagon.V6.vsubhnq.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3) #2
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%v5 = tail call <32 x i32> @llvm.hexagon.V6.vavguh.128B(<32 x i32> %v3, <32 x i32> %v2) #2
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br label %b4
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b5: ; preds = %b0
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ret i32 0
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}
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; Function Attrs: nounwind
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declare void @f1(i8* nocapture readonly, i8* nocapture readonly, i8* nocapture, i32, i32, %s.0* nocapture readonly) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vd0.128B() #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vsubhnq.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vavguh.128B(<32 x i32>, <32 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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