107 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			107 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			LLVM
		
	
	
	
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define i64 @test1(i8* %data) {
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; CHECK-LABEL: test1:
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; CHECK:       movzbl
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; CHECK-NEXT:  shlq
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; CHECK-NEXT:  andl
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; CHECK-NEXT:  retq
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %bf.clear = shl i8 %bf.load, 2
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  %0 = and i8 %bf.clear, 60
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  %mul = zext i8 %0 to i64
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  ret i64 %mul
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}
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define i8* @test2(i8* %data) {
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; CHECK-LABEL: test2:
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; CHECK:       movzbl
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; CHECK-NEXT:  andl
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; CHECK-NEXT:  leaq
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; CHECK-NEXT:  retq
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %bf.clear = shl i8 %bf.load, 2
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  %0 = and i8 %bf.clear, 60
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  %mul = zext i8 %0 to i64
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  %add.ptr = getelementptr inbounds i8, i8* %data, i64 %mul
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  ret i8* %add.ptr
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}
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; If the shift op is SHL, the logic op can only be AND.
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define i64 @test3(i8* %data) {
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; CHECK-LABEL: test3:
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; CHECK:       movb
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; CHECK-NEXT:  shlb
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; CHECK-NEXT:  xorb
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; CHECK-NEXT:  movzbl
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; CHECK-NEXT:  retq
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %bf.clear = shl i8 %bf.load, 2
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  %0 = xor i8 %bf.clear, 60
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  %mul = zext i8 %0 to i64
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  ret i64 %mul
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}
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define i64 @test4(i8* %data) {
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; CHECK-LABEL: test4:
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; CHECK:       movzbl
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; CHECK-NEXT:  shrq
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; CHECK-NEXT:  andl
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; CHECK-NEXT:  retq
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %bf.clear = lshr i8 %bf.load, 2
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  %0 = and i8 %bf.clear, 60
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  %1 = zext i8 %0 to i64
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  ret i64 %1
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}
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define i64 @test5(i8* %data) {
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; CHECK-LABEL: test5:
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; CHECK:       movzbl
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; CHECK-NEXT:  shrq
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; CHECK-NEXT:  xorq
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; CHECK-NEXT:  retq
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %bf.clear = lshr i8 %bf.load, 2
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  %0 = xor i8 %bf.clear, 60
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  %1 = zext i8 %0 to i64
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  ret i64 %1
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}
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define i64 @test6(i8* %data) {
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; CHECK-LABEL: test6:
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; CHECK:       movzbl
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; CHECK-NEXT:  shrq
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; CHECK-NEXT:  orq
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; CHECK-NEXT:  retq
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %bf.clear = lshr i8 %bf.load, 2
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  %0 = or i8 %bf.clear, 60
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  %1 = zext i8 %0 to i64
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  ret i64 %1
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}
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; Load is folded with sext.
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define i64 @test8(i8* %data) {
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; CHECK-LABEL: test8:
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; CHECK:       movsbl
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; CHECK-NEXT:  movzwl
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; CHECK-NEXT:  shrl
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; CHECK-NEXT:  orl
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entry:
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  %bf.load = load i8, i8* %data, align 4
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  %ext = sext i8 %bf.load to i16
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  %bf.clear = lshr i16 %ext, 2
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  %0 = or i16 %bf.clear, 60
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  %1 = zext i16 %0 to i64
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  ret i64 %1
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}
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