34 lines
1.0 KiB
ArmAsm
34 lines
1.0 KiB
ArmAsm
//===-- floatunssidfvfp.S - Implement floatunssidfvfp ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../assembly.h"
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//
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// extern double __floatunssidfvfp(unsigned int a);
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//
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// Converts a 32-bit int to a double precision float.
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// Uses Darwin calling convention where a double precision result is
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// return in GPR register pair.
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//
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.syntax unified
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__floatunssidfvfp)
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#if defined(COMPILER_RT_ARMHF_TARGET)
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vmov s0, r0
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vcvt.f64.u32 d0, s0
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#else
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vmov s15, r0 // move int to float register s15
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vcvt.f64.u32 d7, s15 // convert 32-bit int in s15 to double in d7
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vmov r0, r1, d7 // move d7 to result register pair r0/r1
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#endif
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bx lr
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END_COMPILERRT_FUNCTION(__floatunssidfvfp)
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NO_EXEC_STACK_DIRECTIVE
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