168 lines
5.2 KiB
LLVM
168 lines
5.2 KiB
LLVM
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}s_add_i32:
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define amdgpu_kernel void @s_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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%a = load i32, i32 addrspace(1)* %in
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%b = load i32, i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v2i32:
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define amdgpu_kernel void @s_add_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1)* %in
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%b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
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%result = add <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v4i32:
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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define amdgpu_kernel void @s_add_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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%b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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%result = add <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v8i32:
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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define amdgpu_kernel void @s_add_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
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entry:
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%0 = add <8 x i32> %a, %b
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store <8 x i32> %0, <8 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_add_v16i32:
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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; EG: ADD_INT
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define amdgpu_kernel void @s_add_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
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entry:
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%0 = add <16 x i32> %a, %b
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store <16 x i32> %0, <16 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_add_i32:
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define amdgpu_kernel void @v_add_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1
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%a = load volatile i32, i32 addrspace(1)* %gep
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%b = load volatile i32, i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_add_imm_i32:
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define amdgpu_kernel void @v_add_imm_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
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%b_ptr = getelementptr i32, i32 addrspace(1)* %gep, i32 1
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%a = load volatile i32, i32 addrspace(1)* %gep
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%result = add i32 %a, 123
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}add64:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]
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; EG-DAG: ADD_INT {{[* ]*}}
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; EG-DAG: ADDC_UINT
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; EG-DAG: ADD_INT
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; EG-DAG: ADD_INT {{[* ]*}}
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; EG-NOT: SUB
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define amdgpu_kernel void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%add = add i64 %a, %b
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store i64 %add, i64 addrspace(1)* %out
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ret void
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}
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; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
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; use VCC. The test is designed so that %a will be stored in an SGPR and
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; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
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; to a VGPR before doing the add.
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; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]
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; EG-DAG: ADD_INT {{[* ]*}}
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; EG-DAG: ADDC_UINT
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; EG-DAG: ADD_INT
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; EG-DAG: ADD_INT {{[* ]*}}
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; EG-NOT: SUB
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define amdgpu_kernel void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64, i64 addrspace(1)* %in
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%1 = add i64 %a, %0
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; Test i64 add inside a branch.
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; FUNC-LABEL: {{^}}add64_in_branch:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]
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; EG-DAG: ADD_INT {{[* ]*}}
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; EG-DAG: ADDC_UINT
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; EG-DAG: ADD_INT
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; EG-DAG: ADD_INT {{[* ]*}}
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; EG-NOT: SUB
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define amdgpu_kernel void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i64, i64 addrspace(1)* %in
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br label %endif
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else:
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%2 = add i64 %a, %b
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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