239 lines
10 KiB
LLVM
239 lines
10 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,CIVI,GCN %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI,CIVI,GCN %s
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; GCN-LABEL: {{^}}s_abs_v2i16:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
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; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
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; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
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; CIVI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
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; CIVI: s_sub_i32
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; CIVI: s_sub_i32
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; CIVI: s_max_i32
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; CIVI: s_max_i32
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; CIVI: s_add_i32
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; CIVI-DAG: s_add_i32
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; CIVI-DAG: s_and_b32
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; CIVI-DAG: s_or_b32
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define amdgpu_kernel void @s_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 {
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%neg = sub <2 x i16> zeroinitializer, %val
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%cond = icmp sgt <2 x i16> %val, %neg
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%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
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%res2 = add <2 x i16> %res, <i16 2, i16 2>
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store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_abs_v2i16:
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; GFX9: global_load_dword [[VAL:v[0-9]+]]
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; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
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; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
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; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
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; VI-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
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; VI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16,
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; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; VI-DAG: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
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; VI-DAG: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI-DAG: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u16_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}
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; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[TWO]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
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; VI-NOT: v_and_b32
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; VI: v_or_b32_e32
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; CI: buffer_load_dword v
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; CI: v_lshrrev_b32_e32
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; CI-DAG: v_sub_i32_e32
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; CI-DAG: v_bfe_i32
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; CI-DAG: v_bfe_i32
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; CI-DAG: v_max_i32
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; CI-DAG: v_max_i32
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; CI-DAG: v_add_i32
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; CI-DAG: v_add_i32
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; CI-DAG: v_or_b32
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define amdgpu_kernel void @v_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid
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%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
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%val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4
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%neg = sub <2 x i16> zeroinitializer, %val
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%cond = icmp sgt <2 x i16> %val, %neg
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%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
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%res2 = add <2 x i16> %res, <i16 2, i16 2>
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store <2 x i16> %res2, <2 x i16> addrspace(1)* %gep.out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_abs_v2i16_2:
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; GFX9: s_load_dword [[VAL:s[0-9]+]]
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; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
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; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
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; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
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define amdgpu_kernel void @s_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 {
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%z0 = insertelement <2 x i16> undef, i16 0, i16 0
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%z1 = insertelement <2 x i16> %z0, i16 0, i16 1
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%t0 = insertelement <2 x i16> undef, i16 2, i16 0
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%t1 = insertelement <2 x i16> %t0, i16 2, i16 1
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%neg = sub <2 x i16> %z1, %val
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%cond = icmp sgt <2 x i16> %val, %neg
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%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
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%res2 = add <2 x i16> %res, %t1
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store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_abs_v2i16_2:
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; GFX9: global_load_dword [[VAL:v[0-9]+]]
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; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
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; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
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; GFX9: v_pk_sub_u16 [[ADD:v[0-9]+]], [[MAX]], -2 op_sel_hi:[1,0]
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define amdgpu_kernel void @v_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
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%z0 = insertelement <2 x i16> undef, i16 0, i16 0
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%z1 = insertelement <2 x i16> %z0, i16 0, i16 1
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%t0 = insertelement <2 x i16> undef, i16 2, i16 0
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%t1 = insertelement <2 x i16> %t0, i16 2, i16 1
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid
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%val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4
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%neg = sub <2 x i16> %z1, %val
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%cond = icmp sgt <2 x i16> %val, %neg
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%res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
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%res2 = add <2 x i16> %res, %t1
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store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_abs_v4i16:
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; GFX9: s_load_dwordx2 s{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}, s[0:1], 0x2c
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; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]]
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; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]]
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; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]]
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; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]]
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; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0]
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; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0]
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define amdgpu_kernel void @s_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %val) #0 {
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%z0 = insertelement <4 x i16> undef, i16 0, i16 0
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%z1 = insertelement <4 x i16> %z0, i16 0, i16 1
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%z2 = insertelement <4 x i16> %z1, i16 0, i16 2
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%z3 = insertelement <4 x i16> %z2, i16 0, i16 3
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%t0 = insertelement <4 x i16> undef, i16 2, i16 0
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%t1 = insertelement <4 x i16> %t0, i16 2, i16 1
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%t2 = insertelement <4 x i16> %t1, i16 2, i16 2
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%t3 = insertelement <4 x i16> %t2, i16 2, i16 3
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%neg = sub <4 x i16> %z3, %val
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%cond = icmp sgt <4 x i16> %val, %neg
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%res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
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%res2 = add <4 x i16> %res, %t3
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store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_abs_v4i16:
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; GFX9: global_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
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; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]]
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; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]]
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; GFX9-DAG: v_pk_sub_u16 [[ADD0:v[0-9]+]], [[MAX0]], -2 op_sel_hi:[1,0]
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; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]]
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; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]]
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; GFX9-DAG: v_pk_sub_u16 [[ADD1:v[0-9]+]], [[MAX1]], -2 op_sel_hi:[1,0]
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define amdgpu_kernel void @v_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %src) #0 {
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%z0 = insertelement <4 x i16> undef, i16 0, i16 0
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%z1 = insertelement <4 x i16> %z0, i16 0, i16 1
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%z2 = insertelement <4 x i16> %z1, i16 0, i16 2
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%z3 = insertelement <4 x i16> %z2, i16 0, i16 3
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%t0 = insertelement <4 x i16> undef, i16 2, i16 0
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%t1 = insertelement <4 x i16> %t0, i16 2, i16 1
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%t2 = insertelement <4 x i16> %t1, i16 2, i16 2
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%t3 = insertelement <4 x i16> %t2, i16 2, i16 3
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %src, i32 %tid
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%val = load <4 x i16>, <4 x i16> addrspace(1)* %gep.in, align 4
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%neg = sub <4 x i16> %z3, %val
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%cond = icmp sgt <4 x i16> %val, %neg
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%res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
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%res2 = add <4 x i16> %res, %t3
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store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_min_max_v2i16:
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; GFX9: v_pk_max_i16
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; GFX9: v_pk_min_i16
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define amdgpu_kernel void @s_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) #0 {
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%cond0 = icmp sgt <2 x i16> %val0, %val1
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%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
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%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
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store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
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store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_min_max_v2i16:
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; GFX9: v_pk_max_i16
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; GFX9: v_pk_min_i16
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define amdgpu_kernel void @v_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 {
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%val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
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%val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1
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%cond0 = icmp sgt <2 x i16> %val0, %val1
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%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
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%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
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store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
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store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_min_max_v4i16:
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; GFX9-DAG: v_pk_max_i16
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; GFX9-DAG: v_pk_min_i16
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; GFX9-DAG: v_pk_max_i16
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; GFX9-DAG: v_pk_min_i16
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define amdgpu_kernel void @s_min_max_v4i16(<4 x i16> addrspace(1)* %out0, <4 x i16> addrspace(1)* %out1, <4 x i16> %val0, <4 x i16> %val1) #0 {
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%cond0 = icmp sgt <4 x i16> %val0, %val1
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%sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1
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%sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0
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store volatile <4 x i16> %sel0, <4 x i16> addrspace(1)* %out0, align 4
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store volatile <4 x i16> %sel1, <4 x i16> addrspace(1)* %out1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}v_min_max_v2i16_user:
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define amdgpu_kernel void @v_min_max_v2i16_user(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 {
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%val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
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%val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1
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%cond0 = icmp sgt <2 x i16> %val0, %val1
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%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
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%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
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store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
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store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
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store volatile <2 x i1> %cond0, <2 x i1> addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}u_min_max_v2i16:
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; GFX9: v_pk_max_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_pk_min_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @u_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) nounwind {
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%cond0 = icmp ugt <2 x i16> %val0, %val1
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%sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
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%sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
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store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
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store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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