165 lines
7.4 KiB
LLVM
165 lines
7.4 KiB
LLVM
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mtriple=r600-- -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s
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; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-promote-alloca,sroa,instcombine < %s | FileCheck -check-prefix=OPT %s
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target datalayout = "A5"
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; OPT-LABEL: @vector_read(
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; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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; OPT: store i32 %0, i32 addrspace(1)* %out, align 4
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; FUNC-LABEL: {{^}}vector_read:
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOVA_INT
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define amdgpu_kernel void @vector_read(i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32 addrspace(5)* %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @vector_write(
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; OPT: %0 = insertelement <4 x i32> zeroinitializer, i32 1, i32 %w_index
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; OPT: %1 = extractelement <4 x i32> %0, i32 %r_index
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; OPT: store i32 %1, i32 addrspace(1)* %out, align 4
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; FUNC-LABEL: {{^}}vector_write:
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOV
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; EG: MOVA_INT
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; EG: MOVA_INT
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define amdgpu_kernel void @vector_write(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 0, i32 addrspace(5)* %y
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store i32 0, i32 addrspace(5)* %z
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store i32 0, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %w_index
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store i32 1, i32 addrspace(5)* %tmp1
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%tmp2 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %r_index
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%tmp3 = load i32, i32 addrspace(5)* %tmp2
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store i32 %tmp3, i32 addrspace(1)* %out
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ret void
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}
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; This test should be optimize to:
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; store i32 0, i32 addrspace(1)* %out
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; OPT-LABEL: @bitcast_gep(
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; OPT-LABEL: store i32 0, i32 addrspace(1)* %out, align 4
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; FUNC-LABEL: {{^}}bitcast_gep:
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; EG: STORE_RAW
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define amdgpu_kernel void @bitcast_gep(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 0, i32 addrspace(5)* %y
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store i32 0, i32 addrspace(5)* %z
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store i32 0, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%tmp2 = bitcast i32 addrspace(5)* %tmp1 to [4 x i32] addrspace(5)*
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%tmp3 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp2, i32 0, i32 0
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%tmp4 = load i32, i32 addrspace(5)* %tmp3
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store i32 %tmp4, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @vector_read_bitcast_gep(
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; OPT: %0 = extractelement <4 x i32> <i32 1065353216, i32 1, i32 2, i32 3>, i32 %index
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; OPT: store i32 %0, i32 addrspace(1)* %out, align 4
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define amdgpu_kernel void @vector_read_bitcast_gep(i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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%bc = bitcast i32 addrspace(5)* %x to float addrspace(5)*
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store float 1.0, float addrspace(5)* %bc
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32 addrspace(5)* %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: Should be able to promote this. Instcombine should fold the
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; cast in the hasOneUse case so it might not matter in practice
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; OPT-LABEL: @vector_read_bitcast_alloca(
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; OPT: alloca [4 x float]
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; OPT: store float
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; OPT: store float
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; OPT: store float
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; OPT: store float
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; OPT: load float
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define amdgpu_kernel void @vector_read_bitcast_alloca(float addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%tmp.bc = bitcast [4 x i32] addrspace(5)* %tmp to [4 x float] addrspace(5)*
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%x = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 0
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%y = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 1
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%z = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 2
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%w = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 3
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store float 0.0, float addrspace(5)* %x
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store float 1.0, float addrspace(5)* %y
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store float 2.0, float addrspace(5)* %z
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store float 4.0, float addrspace(5)* %w
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%tmp1 = getelementptr inbounds [4 x float], [4 x float] addrspace(5)* %tmp.bc, i32 0, i32 %index
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%tmp2 = load float, float addrspace(5)* %tmp1
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store float %tmp2, float addrspace(1)* %out
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ret void
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}
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; The pointer arguments in local address space should not affect promotion to vector.
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; OPT-LABEL: @vector_read_with_local_arg(
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; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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; OPT: store i32 %0, i32 addrspace(1)* %out, align 4
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define amdgpu_kernel void @vector_read_with_local_arg(i32 addrspace(3)* %stopper, i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 0
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32 addrspace(5)* %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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