60 lines
1.8 KiB
LLVM
60 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=armebv7 -target-abi apcs -o - %s | FileCheck %s
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@vec6_p = external global <6 x i16>
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define i32 @vec_to_int() {
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; CHECK-LABEL: vec_to_int:
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; CHECK: @ %bb.0: @ %bb.0
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; CHECK-NEXT: push {r4}
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; CHECK-NEXT: sub sp, sp, #28
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; CHECK-NEXT: movw r0, :lower16:vec6_p
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; CHECK-NEXT: movt r0, :upper16:vec6_p
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; CHECK-NEXT: vld1.8 {d16}, [r0]!
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: @ implicit-def: $d17
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; CHECK-NEXT: vmov.32 d17[0], r0
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; CHECK-NEXT: vrev32.16 d18, d17
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; CHECK-NEXT: vrev16.8 d16, d16
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; CHECK-NEXT: @ kill: def $d16 killed $d16 def $q8
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; CHECK-NEXT: vmov.f64 d17, d18
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; CHECK-NEXT: vstmia sp, {d16, d17} @ 16-byte Spill
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; CHECK-NEXT: b .LBB0_1
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; CHECK-NEXT: .LBB0_1: @ %bb.1
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; CHECK-NEXT: vldmia sp, {d16, d17} @ 16-byte Reload
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; CHECK-NEXT: vrev32.16 q8, q8
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; CHECK-NEXT: vmov.f64 d16, d17
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; CHECK-NEXT: vmov.32 r0, d16[0]
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; CHECK-NEXT: add sp, sp, #28
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; CHECK-NEXT: pop {r4}
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; CHECK-NEXT: bx lr
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bb.0:
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%vec6 = load <6 x i16>, <6 x i16>* @vec6_p, align 1
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br label %bb.1
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bb.1:
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%0 = bitcast <6 x i16> %vec6 to i96
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%1 = trunc i96 %0 to i32
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ret i32 %1
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}
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define i16 @int_to_vec(i80 %in) {
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; CHECK-LABEL: int_to_vec:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: @ kill: def $r2 killed $r1
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; CHECK-NEXT: @ kill: def $r2 killed $r0
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; CHECK-NEXT: lsl r0, r0, #16
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; CHECK-NEXT: orr r0, r0, r1, lsr #16
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; CHECK-NEXT: @ implicit-def: $d18
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; CHECK-NEXT: vmov.32 d18[0], r0
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; CHECK-NEXT: @ implicit-def: $q8
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; CHECK-NEXT: vmov.f64 d16, d18
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; CHECK-NEXT: vrev32.16 q8, q8
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; CHECK-NEXT: @ kill: def $d16 killed $d16 killed $q8
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; CHECK-NEXT: vmov.u16 r0, d16[0]
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; CHECK-NEXT: bx lr
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%vec = bitcast i80 %in to <5 x i16>
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%e0 = extractelement <5 x i16> %vec, i32 0
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ret i16 %e0
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}
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