247 lines
9.7 KiB
LLVM
247 lines
9.7 KiB
LLVM
; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,ISBDSB -dump-input-context=100
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; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB -dump-input-context=100
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; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,SB -dump-input-context=100
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; RUN: llc -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,SB -dump-input-context=100
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; RUN: llc -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,NOHARDENARM -dump-input-context=100
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; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,NOHARDENTHUMB
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; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,ISBDSB
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; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB
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; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,SB
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; RUN: llc -global-isel -global-isel-abort=0 -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,SB
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; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,ISBDSB
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; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,ISBDSB
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; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,ARM,HARDEN,SB
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; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,HARDENTHUMB,HARDEN,SB
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; Function Attrs: norecurse nounwind readnone
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define dso_local i32 @double_return(i32 %a, i32 %b) local_unnamed_addr {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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; Make a very easy, very likely to predicate return (BX LR), to test that
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; it will not get predicated when sls-hardening is enabled.
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%mul = mul i32 %b, %a
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ret i32 %mul
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; CHECK-LABEL: double_return:
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; HARDEN: {{bx lr$}}
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; NOHARDENARM: {{bxge lr$}}
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; NOHARDENTHUMB: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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if.else: ; preds = %entry
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%div3 = sdiv i32 %a, %b
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%div2 = sdiv i32 %a, %div3
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%div1 = sdiv i32 %a, %div2
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ret i32 %div1
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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}
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@__const.indirect_branch.ptr = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@indirect_branch, %return), i8* blockaddress(@indirect_branch, %l2)], align 8
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; Function Attrs: norecurse nounwind readnone
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define dso_local i32 @indirect_branch(i32 %a, i32 %b, i32 %i) {
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; CHECK-LABEL: indirect_branch:
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entry:
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @__const.indirect_branch.ptr, i64 0, i64 %idxprom
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%0 = load i8*, i8** %arrayidx, align 8
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indirectbr i8* %0, [label %return, label %l2]
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; ARM: bx r0
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; THUMB: mov pc, r0
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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l2: ; preds = %entry
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br label %return
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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return: ; preds = %entry, %l2
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%retval.0 = phi i32 [ 1, %l2 ], [ 0, %entry ]
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ret i32 %retval.0
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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}
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define i32 @asmgoto() {
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entry:
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; CHECK-LABEL: asmgoto:
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callbr void asm sideeffect "B $0", "X"(i8* blockaddress(@asmgoto, %d))
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to label %asm.fallthrough [label %d]
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; The asm goto above produces a direct branch:
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; CHECK: @APP
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; CHECK-NEXT: {{^[ \t]+b }}
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; CHECK-NEXT: @NO_APP
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; For direct branches, no mitigation is needed.
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; ISDDSB-NOT: dsb sy
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; SB-NOT: {{ sb$}}
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asm.fallthrough: ; preds = %entry
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ret i32 0
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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d: ; preds = %asm.fallthrough, %entry
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ret i32 1
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK-NEXT: .Lfunc_end
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}
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; Check that indirect branches produced through switch jump tables are also
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; hardened:
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define dso_local i32 @jumptable(i32 %a, i32 %b) {
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; CHECK-LABEL: jumptable:
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entry:
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switch i32 %b, label %sw.epilog [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 3, label %sw.bb3
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i32 4, label %sw.bb5
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]
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; ARM: ldr pc, [{{r[0-9]}}, {{r[0-9]}}, lsl #2]
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; NOHARDENTHUMB: tbb [pc, {{r[0-9]}}]
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; HARDENTHUMB: mov pc, {{r[0-9]}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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sw.bb: ; preds = %entry
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%add = shl nsw i32 %a, 1
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br label %sw.bb1
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sw.bb1: ; preds = %entry, %sw.bb
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%a.addr.0 = phi i32 [ %a, %entry ], [ %add, %sw.bb ]
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%add2 = shl nsw i32 %a.addr.0, 1
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br label %sw.bb3
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sw.bb3: ; preds = %entry, %sw.bb1
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%a.addr.1 = phi i32 [ %a, %entry ], [ %add2, %sw.bb1 ]
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%add4 = shl nsw i32 %a.addr.1, 1
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br label %sw.bb5
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sw.bb5: ; preds = %entry, %sw.bb3
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%a.addr.2 = phi i32 [ %a, %entry ], [ %add4, %sw.bb3 ]
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%add6 = shl nsw i32 %a.addr.2, 1
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb5, %entry
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%a.addr.3 = phi i32 [ %a, %entry ], [ %add6, %sw.bb5 ]
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ret i32 %a.addr.3
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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}
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define dso_local i32 @indirect_call(
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i32 (...)* nocapture %f1, i32 (...)* nocapture %f2) {
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entry:
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; CHECK-LABEL: indirect_call:
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%callee.knr.cast = bitcast i32 (...)* %f1 to i32 ()*
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%call = tail call i32 %callee.knr.cast()
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; HARDENARM: bl {{__llvm_slsblr_thunk_arm_r[0-9]+$}}
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; HARDENTHUMB: bl {{__llvm_slsblr_thunk_thumb_r[0-9]+$}}
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%callee.knr.cast1 = bitcast i32 (...)* %f2 to i32 ()*
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%call2 = tail call i32 %callee.knr.cast1()
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; HARDENARM: bl {{__llvm_slsblr_thunk_arm_r[0-9]+$}}
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; HARDENTHUMB: bl {{__llvm_slsblr_thunk_thumb_r[0-9]+$}}
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%add = add nsw i32 %call2, %call
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ret i32 %add
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; CHECK: .Lfunc_end
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}
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; verify calling through a function pointer.
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@a = dso_local local_unnamed_addr global i32 (...)* null, align 8
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@b = dso_local local_unnamed_addr global i32 0, align 4
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define dso_local void @indirect_call_global() local_unnamed_addr {
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; CHECK-LABEL: indirect_call_global:
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entry:
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%0 = load i32 ()*, i32 ()** bitcast (i32 (...)** @a to i32 ()**), align 8
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%call = tail call i32 %0() nounwind
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; HARDENARM: bl {{__llvm_slsblr_thunk_arm_r[0-9]+$}}
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; HARDENTHUMB: bl {{__llvm_slsblr_thunk_thumb_r[0-9]+$}}
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store i32 %call, i32* @b, align 4
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ret void
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; CHECK: .Lfunc_end
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}
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; Verify that neither r12 nor lr are used as registers in indirect call
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; instructions when the sls-hardening-blr mitigation is enabled, as
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; (a) a linker is allowed to clobber r12 on calls, and
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; (b) the hardening transformation isn't correct if lr is the register holding
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; the address of the function called.
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define i32 @check_r12(i32 ()** %fp) {
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entry:
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; CHECK-LABEL: check_r12:
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%f = load i32 ()*, i32 ()** %fp, align 4
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; Force f to be moved into r12
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%r12_f = tail call i32 ()* asm "add $0, $1, #0", "={r12},{r12}"(i32 ()* %f) nounwind
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%call = call i32 %r12_f()
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; NOHARDENARM: blx r12
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; NOHARDENTHUMB: blx r12
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; HARDEN-NOT: bl {{__llvm_slsblr_thunk_(arm|thumb)_r12}}
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ret i32 %call
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; CHECK: .Lfunc_end
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}
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define i32 @check_lr(i32 ()** %fp) {
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entry:
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; CHECK-LABEL: check_lr:
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%f = load i32 ()*, i32 ()** %fp, align 4
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; Force f to be moved into lr
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%lr_f = tail call i32 ()* asm "add $0, $1, #0", "={lr},{lr}"(i32 ()* %f) nounwind
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%call = call i32 %lr_f()
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; NOHARDENARM: blx lr
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; NOHARDENTHUMB: blx lr
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; HARDEN-NOT: bl {{__llvm_slsblr_thunk_(arm|thumb)_lr}}
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ret i32 %call
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; CHECK: .Lfunc_end
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}
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; Verify that even when sls-harden-blr is enabled, "blx r12" is still an
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; instruction that is accepted by the inline assembler
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define void @verify_inline_asm_blx_r12(void ()* %g) {
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entry:
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; CHECK-LABEL: verify_inline_asm_blx_r12:
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%0 = bitcast void ()* %g to i8*
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tail call void asm sideeffect "blx $0", "{r12}"(i8* %0) nounwind
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; CHECK: blx r12
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ret void
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; CHECK: {{bx lr$}}
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: {{ sb$}}
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; CHECK: .Lfunc_end
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}
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; HARDEN-label: {{__llvm_slsblr_thunk_(arm|thumb)_r5}}:
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; HARDEN: bx r5
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; ISBDSB-NEXT: dsb sy
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; ISBDSB-NEXT: isb
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; SB-NEXT: dsb sy
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; SB-NEXT: isb
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; HARDEN-NEXT: .Lfunc_end
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