68 lines
2.9 KiB
LLVM
68 lines
2.9 KiB
LLVM
; RUN: llc -march=hexagon -O2 -debug-only=pipeliner -hexagon-initial-cfg-cleanup=0 < %s -o - 2>&1 > /dev/null | FileCheck %s
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; REQUIRES: asserts
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; Test that the phi in the first epilog block is getter the correct
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; value from the kernel block. In this bug, the phi was using the value
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; defined in the loop instead of the Phi valued defined in the kernel.
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; We need to use the kernel's phi value (if the Phi in the kernel is the
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; last definition).
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; CHECK: New block
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; CHECK: %[[REG:([0-9]+)]]:intregs = PHI %{{.*}}, %[[REG1:([0-9]+)]]
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; CHECK: %[[REG1]]:intregs = nuw A2_addi
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; CHECK: epilog:
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; CHECK: %{{[0-9]+}}:intregs = PHI %{{.*}}, %[[REG]]
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define void @f0(i32 %a0, i32 %a1) #0 {
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b0:
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%v0 = icmp sgt i32 %a0, 64
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br i1 %v0, label %b1, label %b3
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b1: ; preds = %b0
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br label %b2
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b2: ; preds = %b2, %b1
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%v1 = phi i32 [ %a0, %b1 ], [ %v13, %b2 ]
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%v2 = phi <16 x i32>* [ null, %b1 ], [ %v3, %b2 ]
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%v3 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
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%v4 = load <16 x i32>, <16 x i32>* %v2, align 64
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%v5 = load <16 x i32>, <16 x i32>* undef, align 64
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%v6 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v5, <16 x i32> undef, i32 1)
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%v7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> undef, <16 x i32> %v6)
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%v8 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v7, i32 undef)
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%v9 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v8, <32 x i32> undef, i32 undef)
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%v10 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v9, <16 x i32> zeroinitializer, i32 undef)
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%v11 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v10)
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%v12 = tail call <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32> undef, <16 x i32> %v11, i32 %a1)
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store <16 x i32> %v12, <16 x i32>* null, align 64
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%v13 = add nsw i32 %v1, -64
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%v14 = icmp sgt i32 %v13, 64
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br i1 %v14, label %b2, label %b3
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b3: ; preds = %b2, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vasrhubsat(<16 x i32>, <16 x i32>, i32) #0
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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