68 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			68 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			LLVM
		
	
	
	
| ; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
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| 
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| ; Test that when we order instructions in a packet we check for
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| ; order dependences so that the source of an order dependence
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| ; appears before the destination.
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| 
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| ; CHECK: loop0(.LBB0_[[LOOP:.]],
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| ; CHECK: .LBB0_[[LOOP]]:
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| ; CHECK: = memw
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| ; CHECK: = memw
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| ; CHECK: memw({{.*}}) =
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| ; CHECK: = memw
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| ; CHECK: = memw
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| ; CHECK: endloop0
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| 
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| @g0 = external hidden unnamed_addr constant [19 x i8], align 1
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| 
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| ; Function Attrs: nounwind optsize
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| declare i32 @f0(i8* nocapture readonly, ...) #0
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| 
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| ; Function Attrs: nounwind optsize
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| declare void @f1(i32*, i32*, i32* nocapture readnone) #0
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| 
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| ; Function Attrs: argmemonly nounwind
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| declare i8* @llvm.hexagon.circ.stw(i8*, i32, i32, i32) #1
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| 
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| ; Function Attrs: nounwind optsize
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| define void @f2(i32* %a0, i32* %a1, i32* %a2) #0 {
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| b0:
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|   %v0 = alloca i32, align 4
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|   call void @f1(i32* %a2, i32* %a0, i32* %v0) #2
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|   %v1 = bitcast i32* %a1 to i8*
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|   br label %b1
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| 
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| b1:                                               ; preds = %b1, %b0
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|   %v2 = phi i32 [ 0, %b0 ], [ %v13, %b1 ]
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|   %v3 = phi i32* [ %a2, %b0 ], [ %v16, %b1 ]
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|   %v4 = phi i32 [ 0, %b0 ], [ %v14, %b1 ]
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|   %v5 = load i32, i32* %a1, align 4, !tbaa !0
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|   %v6 = add nsw i32 %v2, %v5
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|   %v7 = load i32, i32* %v3, align 4, !tbaa !0
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|   %v8 = tail call i8* @llvm.hexagon.circ.stw(i8* %v1, i32 %v7, i32 150995968, i32 4) #3
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|   %v9 = bitcast i8* %v8 to i32*
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|   %v10 = load i32, i32* %v3, align 4, !tbaa !0
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|   %v11 = add nsw i32 %v6, %v10
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|   %v12 = load i32, i32* %v9, align 4, !tbaa !0
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|   %v13 = add nsw i32 %v11, %v12
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|   %v14 = add nsw i32 %v4, 1
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|   %v15 = icmp eq i32 %v14, 2
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|   %v16 = getelementptr i32, i32* %v3, i32 1
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|   br i1 %v15, label %b2, label %b1
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| 
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| b2:                                               ; preds = %b1
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|   %v17 = tail call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([19 x i8], [19 x i8]* @g0, i32 0, i32 0), i32 %v13) #4
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|   ret void
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| }
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| 
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| attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }
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| attributes #1 = { argmemonly nounwind }
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| attributes #2 = { optsize }
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| attributes #3 = { nounwind }
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| attributes #4 = { nounwind optsize }
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| 
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| !0 = !{!1, !1, i64 0}
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| !1 = !{!"int", !2, i64 0}
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| !2 = !{!"omnipotent char", !3, i64 0}
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| !3 = !{!"Simple C/C++ TBAA"}
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