50 lines
2.0 KiB
LLVM
50 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon -enable-pipeliner -enable-bsb-sched=0 -join-liveintervals=false < %s -pipeliner-experimental-cg=true | FileCheck %s
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; XFAIL: *
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; This test is failing after post-ra machine sinking.
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; Test that we generate the correct Phi values when there is a Phi that
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; references another Phi. We need to examine the other Phi to get the
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; correct value. We need to do this even if we haven't generated the
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; kernel code for the other Phi yet.
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; CHECK: v[[REG0:[0-9]+]] = v[[REG1:[0-9]+]]
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; CHECK: loop0
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; Check for copy REG0 = REG1 (via vcombine):
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; CHECK: v{{[0-9]+}}:[[REG0]] = vcombine(v{{[0-9]+}},v[[REG1]])
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; CHECK: endloop0
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; Function Attrs: nounwind
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define void @f0() #0 {
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b0:
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br i1 undef, label %b1, label %b2
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ]
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%v1 = phi <16 x i32> [ %v4, %b1 ], [ undef, %b0 ]
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%v2 = phi <16 x i32> [ %v1, %b1 ], [ undef, %b0 ]
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%v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v1, <16 x i32> %v2, i32 62)
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%v4 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> undef)
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%v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v1, i32 2)
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%v6 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %v3, <16 x i32> %v5)
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store <16 x i32> %v6, <16 x i32>* null, align 64
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%v7 = add nsw i32 %v0, 1
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%v8 = icmp slt i32 %v7, undef
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br i1 %v8, label %b1, label %b2
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b2: ; preds = %b1, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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