155 lines
5.2 KiB
LLVM
155 lines
5.2 KiB
LLVM
; Test vector intrinsics added with z15.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z15 | FileCheck %s
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declare <16 x i8> @llvm.s390.vsld(<16 x i8>, <16 x i8>, i32)
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declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32)
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declare {<16 x i8>, i32} @llvm.s390.vstrsb(<16 x i8>, <16 x i8>, <16 x i8>)
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declare {<16 x i8>, i32} @llvm.s390.vstrsh(<8 x i16>, <8 x i16>, <16 x i8>)
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declare {<16 x i8>, i32} @llvm.s390.vstrsf(<4 x i32>, <4 x i32>, <16 x i8>)
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declare {<16 x i8>, i32} @llvm.s390.vstrszb(<16 x i8>, <16 x i8>, <16 x i8>)
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declare {<16 x i8>, i32} @llvm.s390.vstrszh(<8 x i16>, <8 x i16>, <16 x i8>)
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declare {<16 x i8>, i32} @llvm.s390.vstrszf(<4 x i32>, <4 x i32>, <16 x i8>)
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; VSLD with the minimum useful value.
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define <16 x i8> @test_vsld_1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_vsld_1:
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; CHECK: vsld %v24, %v24, %v26, 1
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 1)
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ret <16 x i8> %res
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}
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; VSLD with the maximum value.
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define <16 x i8> @test_vsld_7(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_vsld_7:
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; CHECK: vsld %v24, %v24, %v26, 7
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vsld(<16 x i8> %a, <16 x i8> %b, i32 7)
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ret <16 x i8> %res
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}
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; VSRD with the minimum useful value.
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define <16 x i8> @test_vsrd_1(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_vsrd_1:
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; CHECK: vsrd %v24, %v24, %v26, 1
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 1)
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ret <16 x i8> %res
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}
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; VSRD with the maximum value.
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define <16 x i8> @test_vsrd_7(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: test_vsrd_7:
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; CHECK: vsrd %v24, %v24, %v26, 7
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; CHECK: br %r14
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%res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 7)
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ret <16 x i8> %res
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}
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; VSTRSB.
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define <16 x i8> @test_vstrsb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
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i32 *%ccptr) {
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; CHECK-LABEL: test_vstrsb:
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; CHECK: vstrsb %v24, %v24, %v26, %v28, 0
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%call = call {<16 x i8>, i32} @llvm.s390.vstrsb(<16 x i8> %a, <16 x i8> %b,
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<16 x i8> %c)
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%res = extractvalue {<16 x i8>, i32} %call, 0
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%cc = extractvalue {<16 x i8>, i32} %call, 1
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store i32 %cc, i32 *%ccptr
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ret <16 x i8> %res
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}
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; VSTRSH.
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define <16 x i8> @test_vstrsh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c,
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i32 *%ccptr) {
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; CHECK-LABEL: test_vstrsh:
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; CHECK: vstrsh %v24, %v24, %v26, %v28, 0
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%call = call {<16 x i8>, i32} @llvm.s390.vstrsh(<8 x i16> %a, <8 x i16> %b,
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<16 x i8> %c)
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%res = extractvalue {<16 x i8>, i32} %call, 0
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%cc = extractvalue {<16 x i8>, i32} %call, 1
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store i32 %cc, i32 *%ccptr
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ret <16 x i8> %res
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}
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; VSTRSFS.
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define <16 x i8> @test_vstrsf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c,
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i32 *%ccptr) {
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; CHECK-LABEL: test_vstrsf:
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; CHECK: vstrsf %v24, %v24, %v26, %v28, 0
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%call = call {<16 x i8>, i32} @llvm.s390.vstrsf(<4 x i32> %a, <4 x i32> %b,
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<16 x i8> %c)
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%res = extractvalue {<16 x i8>, i32} %call, 0
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%cc = extractvalue {<16 x i8>, i32} %call, 1
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store i32 %cc, i32 *%ccptr
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ret <16 x i8> %res
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}
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; VSTRSZB.
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define <16 x i8> @test_vstrszb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c,
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i32 *%ccptr) {
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; CHECK-LABEL: test_vstrszb:
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; CHECK: vstrszb %v24, %v24, %v26, %v28
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%call = call {<16 x i8>, i32} @llvm.s390.vstrszb(<16 x i8> %a, <16 x i8> %b,
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<16 x i8> %c)
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%res = extractvalue {<16 x i8>, i32} %call, 0
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%cc = extractvalue {<16 x i8>, i32} %call, 1
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store i32 %cc, i32 *%ccptr
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ret <16 x i8> %res
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}
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; VSTRSZH.
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define <16 x i8> @test_vstrszh(<8 x i16> %a, <8 x i16> %b, <16 x i8> %c,
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i32 *%ccptr) {
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; CHECK-LABEL: test_vstrszh:
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; CHECK: vstrszh %v24, %v24, %v26, %v28
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%call = call {<16 x i8>, i32} @llvm.s390.vstrszh(<8 x i16> %a, <8 x i16> %b,
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<16 x i8> %c)
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%res = extractvalue {<16 x i8>, i32} %call, 0
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%cc = extractvalue {<16 x i8>, i32} %call, 1
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store i32 %cc, i32 *%ccptr
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ret <16 x i8> %res
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}
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; VSTRSZF.
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define <16 x i8> @test_vstrszf(<4 x i32> %a, <4 x i32> %b, <16 x i8> %c,
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i32 *%ccptr) {
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; CHECK-LABEL: test_vstrszf:
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; CHECK: vstrszf %v24, %v24, %v26, %v28
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; CHECK: ipm [[REG:%r[0-5]]]
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; CHECK: srl [[REG]], 28
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; CHECK: st [[REG]], 0(%r2)
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; CHECK: br %r14
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%call = call {<16 x i8>, i32} @llvm.s390.vstrszf(<4 x i32> %a, <4 x i32> %b,
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<16 x i8> %c)
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%res = extractvalue {<16 x i8>, i32} %call, 0
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%cc = extractvalue {<16 x i8>, i32} %call, 1
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store i32 %cc, i32 *%ccptr
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ret <16 x i8> %res
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}
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