42 lines
1.2 KiB
LLVM
42 lines
1.2 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test pack intrinsic instructions
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;;;
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;;; Note:
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;;; We test pack_f32p and pack_f32a pseudo instruction.
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; Function Attrs: nounwind readonly
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define fastcc i64 @pack_f32p(float* readonly %0, float* readonly %1) {
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; CHECK-LABEL: pack_f32p:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ldu %s0, (, %s0)
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; CHECK-NEXT: ldl.zx %s1, (, %s1)
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; CHECK-NEXT: or %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = bitcast float* %0 to i8*
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%4 = bitcast float* %1 to i8*
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%5 = tail call i64 @llvm.ve.vl.pack.f32p(i8* %3, i8* %4)
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ret i64 %5
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}
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; Function Attrs: nounwind readonly
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declare i64 @llvm.ve.vl.pack.f32p(i8*, i8*)
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; Function Attrs: nounwind readonly
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define fastcc i64 @pack_f32a(float* readonly %0) {
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; CHECK-LABEL: pack_f32a:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ldl.zx %s0, (, %s0)
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; CHECK-NEXT: lea %s1, 1
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea.sl %s1, 1(, %s1)
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; CHECK-NEXT: mulu.l %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = bitcast float* %0 to i8*
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%3 = tail call i64 @llvm.ve.vl.pack.f32a(i8* %2)
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ret i64 %3
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}
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; Function Attrs: nounwind readonly
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declare i64 @llvm.ve.vl.pack.f32a(i8*)
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