102 lines
3.7 KiB
LLVM
102 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=AVX512DQ
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; Test that we can replace "scalar" FP-bitwise-logic with the optimal instruction.
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; Scalar x86 FP-logic instructions only exist in your imagination and/or the bowels
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; of compilers, but float and double variants of FP-logic instructions are reality
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; and float may be a shorter instruction depending on which flavor of vector ISA
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; you have...so just prefer float all the time, ok? Yay, x86!
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define double @FsANDPSrr(double %x, double %y) {
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; SSE-LABEL: FsANDPSrr:
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; SSE: # %bb.0:
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; SSE-NEXT: andps %xmm1, %xmm0 # encoding: [0x0f,0x54,0xc1]
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; SSE-NEXT: retq # encoding: [0xc3]
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;
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; AVX-LABEL: FsANDPSrr:
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; AVX: # %bb.0:
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x54,0xc1]
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; AVX-NEXT: retq # encoding: [0xc3]
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;
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; AVX512DQ-LABEL: FsANDPSrr:
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; AVX512DQ: # %bb.0:
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; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x54,0xc1]
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; AVX512DQ-NEXT: retq # encoding: [0xc3]
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%bc1 = bitcast double %x to i64
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%bc2 = bitcast double %y to i64
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%and = and i64 %bc1, %bc2
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%bc3 = bitcast i64 %and to double
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ret double %bc3
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}
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define double @FsANDNPSrr(double %x, double %y) {
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; SSE-LABEL: FsANDNPSrr:
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; SSE: # %bb.0:
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; SSE-NEXT: andnps %xmm0, %xmm1 # encoding: [0x0f,0x55,0xc8]
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; SSE-NEXT: movaps %xmm1, %xmm0 # encoding: [0x0f,0x28,0xc1]
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; SSE-NEXT: retq # encoding: [0xc3]
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;
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; AVX-LABEL: FsANDNPSrr:
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; AVX: # %bb.0:
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; AVX-NEXT: vandnps %xmm0, %xmm1, %xmm0 # encoding: [0xc5,0xf0,0x55,0xc0]
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; AVX-NEXT: retq # encoding: [0xc3]
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;
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; AVX512DQ-LABEL: FsANDNPSrr:
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; AVX512DQ: # %bb.0:
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; AVX512DQ-NEXT: vandnps %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf0,0x55,0xc0]
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; AVX512DQ-NEXT: retq # encoding: [0xc3]
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%bc1 = bitcast double %x to i64
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%bc2 = bitcast double %y to i64
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%not = xor i64 %bc2, -1
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%and = and i64 %bc1, %not
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%bc3 = bitcast i64 %and to double
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ret double %bc3
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}
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define double @FsORPSrr(double %x, double %y) {
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; SSE-LABEL: FsORPSrr:
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; SSE: # %bb.0:
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; SSE-NEXT: orps %xmm1, %xmm0 # encoding: [0x0f,0x56,0xc1]
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; SSE-NEXT: retq # encoding: [0xc3]
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;
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; AVX-LABEL: FsORPSrr:
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; AVX: # %bb.0:
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; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x56,0xc1]
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; AVX-NEXT: retq # encoding: [0xc3]
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;
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; AVX512DQ-LABEL: FsORPSrr:
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; AVX512DQ: # %bb.0:
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; AVX512DQ-NEXT: vorps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x56,0xc1]
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; AVX512DQ-NEXT: retq # encoding: [0xc3]
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%bc1 = bitcast double %x to i64
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%bc2 = bitcast double %y to i64
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%or = or i64 %bc1, %bc2
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%bc3 = bitcast i64 %or to double
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ret double %bc3
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}
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define double @FsXORPSrr(double %x, double %y) {
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; SSE-LABEL: FsXORPSrr:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm1, %xmm0 # encoding: [0x0f,0x57,0xc1]
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; SSE-NEXT: retq # encoding: [0xc3]
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;
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; AVX-LABEL: FsXORPSrr:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x57,0xc1]
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; AVX-NEXT: retq # encoding: [0xc3]
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;
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; AVX512DQ-LABEL: FsXORPSrr:
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; AVX512DQ: # %bb.0:
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; AVX512DQ-NEXT: vxorps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x57,0xc1]
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; AVX512DQ-NEXT: retq # encoding: [0xc3]
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%bc1 = bitcast double %x to i64
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%bc2 = bitcast double %y to i64
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%xor = xor i64 %bc1, %bc2
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%bc3 = bitcast i64 %xor to double
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ret double %bc3
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}
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