599 lines
23 KiB
C++
599 lines
23 KiB
C++
//===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that SystemZ uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
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#include "SystemZ.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace SystemZISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Return with a flag operand. Operand 0 is the chain operand.
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RET_FLAG,
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// Calls a function. Operand 0 is the chain operand and operand 1
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// is the target address. The arguments start at operand 2.
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// There is an optional glue operand at the end.
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CALL,
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SIBCALL,
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// TLS calls. Like regular calls, except operand 1 is the TLS symbol.
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// (The call target is implicitly __tls_get_offset.)
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TLS_GDCALL,
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TLS_LDCALL,
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// Wraps a TargetGlobalAddress that should be loaded using PC-relative
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// accesses (LARL). Operand 0 is the address.
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PCREL_WRAPPER,
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// Used in cases where an offset is applied to a TargetGlobalAddress.
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// Operand 0 is the full TargetGlobalAddress and operand 1 is a
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// PCREL_WRAPPER for an anchor point. This is used so that we can
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// cheaply refer to either the full address or the anchor point
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// as a register base.
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PCREL_OFFSET,
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// Integer absolute.
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IABS,
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// Integer comparisons. There are three operands: the two values
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// to compare, and an integer of type SystemZICMP.
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ICMP,
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// Floating-point comparisons. The two operands are the values to compare.
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FCMP,
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// Test under mask. The first operand is ANDed with the second operand
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// and the condition codes are set on the result. The third operand is
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// a boolean that is true if the condition codes need to distinguish
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// between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
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// register forms do but the memory forms don't).
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TM,
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// Branches if a condition is true. Operand 0 is the chain operand;
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// operand 1 is the 4-bit condition-code mask, with bit N in
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// big-endian order meaning "branch if CC=N"; operand 2 is the
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// target block and operand 3 is the flag operand.
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BR_CCMASK,
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// Selects between operand 0 and operand 1. Operand 2 is the
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// mask of condition-code values for which operand 0 should be
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// chosen over operand 1; it has the same form as BR_CCMASK.
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// Operand 3 is the flag operand.
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SELECT_CCMASK,
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// Evaluates to the gap between the stack pointer and the
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// base of the dynamically-allocatable area.
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ADJDYNALLOC,
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// Extracts the value of a 32-bit access register. Operand 0 is
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// the number of the register.
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EXTRACT_ACCESS,
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// Count number of bits set in operand 0 per byte.
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POPCNT,
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// Wrappers around the ISD opcodes of the same name. The output and
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// first input operands are GR128s. The trailing numbers are the
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// widths of the second operand in bits.
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UMUL_LOHI64,
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SDIVREM32,
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SDIVREM64,
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UDIVREM32,
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UDIVREM64,
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// Use a series of MVCs to copy bytes from one memory location to another.
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// The operands are:
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// - the target address
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// - the source address
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// - the constant length
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//
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// This isn't a memory opcode because we'd need to attach two
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// MachineMemOperands rather than one.
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MVC,
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// Like MVC, but implemented as a loop that handles X*256 bytes
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// followed by straight-line code to handle the rest (if any).
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// The value of X is passed as an additional operand.
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MVC_LOOP,
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// Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
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NC,
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NC_LOOP,
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OC,
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OC_LOOP,
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XC,
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XC_LOOP,
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// Use CLC to compare two blocks of memory, with the same comments
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// as for MVC and MVC_LOOP.
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CLC,
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CLC_LOOP,
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// Use an MVST-based sequence to implement stpcpy().
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STPCPY,
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// Use a CLST-based sequence to implement strcmp(). The two input operands
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// are the addresses of the strings to compare.
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STRCMP,
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// Use an SRST-based sequence to search a block of memory. The first
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// operand is the end address, the second is the start, and the third
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// is the character to search for. CC is set to 1 on success and 2
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// on failure.
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SEARCH_STRING,
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// Store the CC value in bits 29 and 28 of an integer.
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IPM,
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// Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
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SERIALIZE,
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// Compiler barrier only; generate a no-op.
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MEMBARRIER,
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// Transaction begin. The first operand is the chain, the second
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// the TDB pointer, and the third the immediate control field.
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// Returns chain and glue.
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TBEGIN,
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TBEGIN_NOFLOAT,
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// Transaction end. Just the chain operand. Returns chain and glue.
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TEND,
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// Create a vector constant by filling byte N of the result with bit
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// 15-N of the single operand.
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BYTE_MASK,
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// Create a vector constant by replicating an element-sized RISBG-style mask.
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// The first operand specifies the starting set bit and the second operand
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// specifies the ending set bit. Both operands count from the MSB of the
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// element.
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ROTATE_MASK,
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// Replicate a GPR scalar value into all elements of a vector.
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REPLICATE,
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// Create a vector from two i64 GPRs.
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JOIN_DWORDS,
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// Replicate one element of a vector into all elements. The first operand
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// is the vector and the second is the index of the element to replicate.
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SPLAT,
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// Interleave elements from the high half of operand 0 and the high half
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// of operand 1.
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MERGE_HIGH,
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// Likewise for the low halves.
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MERGE_LOW,
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// Concatenate the vectors in the first two operands, shift them left
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// by the third operand, and take the first half of the result.
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SHL_DOUBLE,
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// Take one element of the first v2i64 operand and the one element of
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// the second v2i64 operand and concatenate them to form a v2i64 result.
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// The third operand is a 4-bit value of the form 0A0B, where A and B
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// are the element selectors for the first operand and second operands
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// respectively.
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PERMUTE_DWORDS,
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// Perform a general vector permute on vector operands 0 and 1.
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// Each byte of operand 2 controls the corresponding byte of the result,
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// in the same way as a byte-level VECTOR_SHUFFLE mask.
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PERMUTE,
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// Pack vector operands 0 and 1 into a single vector with half-sized elements.
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PACK,
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// Likewise, but saturate the result and set CC. PACKS_CC does signed
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// saturation and PACKLS_CC does unsigned saturation.
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PACKS_CC,
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PACKLS_CC,
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// Unpack the first half of vector operand 0 into double-sized elements.
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// UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
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UNPACK_HIGH,
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UNPACKL_HIGH,
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// Likewise for the second half.
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UNPACK_LOW,
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UNPACKL_LOW,
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// Shift each element of vector operand 0 by the number of bits specified
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// by scalar operand 1.
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VSHL_BY_SCALAR,
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VSRL_BY_SCALAR,
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VSRA_BY_SCALAR,
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// For each element of the output type, sum across all sub-elements of
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// operand 0 belonging to the corresponding element, and add in the
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// rightmost sub-element of the corresponding element of operand 1.
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VSUM,
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// Compare integer vector operands 0 and 1 to produce the usual 0/-1
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// vector result. VICMPE is for equality, VICMPH for "signed greater than"
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// and VICMPHL for "unsigned greater than".
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VICMPE,
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VICMPH,
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VICMPHL,
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// Likewise, but also set the condition codes on the result.
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VICMPES,
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VICMPHS,
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VICMPHLS,
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// Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
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// vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
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// greater than" and VFCMPHE for "ordered and greater than or equal to".
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VFCMPE,
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VFCMPH,
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VFCMPHE,
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// Likewise, but also set the condition codes on the result.
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VFCMPES,
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VFCMPHS,
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VFCMPHES,
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// Test floating-point data class for vectors.
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VFTCI,
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// Extend the even f32 elements of vector operand 0 to produce a vector
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// of f64 elements.
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VEXTEND,
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// Round the f64 elements of vector operand 0 to f32s and store them in the
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// even elements of the result.
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VROUND,
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// AND the two vector operands together and set CC based on the result.
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VTM,
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// String operations that set CC as a side-effect.
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VFAE_CC,
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VFAEZ_CC,
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VFEE_CC,
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VFEEZ_CC,
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VFENE_CC,
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VFENEZ_CC,
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VISTR_CC,
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VSTRC_CC,
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VSTRCZ_CC,
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// Test Data Class.
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//
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// Operand 0: the value to test
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// Operand 1: the bit mask
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TDC,
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// Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
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// ATOMIC_LOAD_<op>.
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//
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// Operand 0: the address of the containing 32-bit-aligned field
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// Operand 1: the second operand of <op>, in the high bits of an i32
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// for everything except ATOMIC_SWAPW
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// Operand 2: how many bits to rotate the i32 left to bring the first
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// operand into the high bits
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// Operand 3: the negative of operand 2, for rotating the other way
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// Operand 4: the width of the field in bits (8 or 16)
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ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
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ATOMIC_LOADW_ADD,
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ATOMIC_LOADW_SUB,
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ATOMIC_LOADW_AND,
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ATOMIC_LOADW_OR,
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ATOMIC_LOADW_XOR,
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ATOMIC_LOADW_NAND,
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ATOMIC_LOADW_MIN,
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ATOMIC_LOADW_MAX,
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ATOMIC_LOADW_UMIN,
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ATOMIC_LOADW_UMAX,
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// A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
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//
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// Operand 0: the address of the containing 32-bit-aligned field
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// Operand 1: the compare value, in the low bits of an i32
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// Operand 2: the swap value, in the low bits of an i32
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// Operand 3: how many bits to rotate the i32 left to bring the first
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// operand into the high bits
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// Operand 4: the negative of operand 2, for rotating the other way
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// Operand 5: the width of the field in bits (8 or 16)
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ATOMIC_CMP_SWAPW,
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// Byte swapping load.
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//
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// Operand 0: the address to load from
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// Operand 1: the type of load (i16, i32, i64)
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LRV,
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// Byte swapping store.
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//
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// Operand 0: the value to store
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// Operand 1: the address to store to
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// Operand 2: the type of store (i16, i32, i64)
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STRV,
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// Prefetch from the second operand using the 4-bit control code in
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// the first operand. The code is 1 for a load prefetch and 2 for
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// a store prefetch.
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PREFETCH
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};
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// Return true if OPCODE is some kind of PC-relative address.
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inline bool isPCREL(unsigned Opcode) {
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return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
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}
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} // end namespace SystemZISD
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namespace SystemZICMP {
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// Describes whether an integer comparison needs to be signed or unsigned,
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// or whether either type is OK.
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enum {
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Any,
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UnsignedOnly,
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SignedOnly
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};
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} // end namespace SystemZICMP
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class SystemZSubtarget;
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class SystemZTargetMachine;
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class SystemZTargetLowering : public TargetLowering {
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public:
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explicit SystemZTargetLowering(const TargetMachine &TM,
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const SystemZSubtarget &STI);
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// Override TargetLowering.
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MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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return MVT::i32;
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}
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MVT getVectorIdxTy(const DataLayout &DL) const override {
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// Only the lower 12 bits of an element index are used, so we don't
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// want to clobber the upper 32 bits of a GPR unnecessarily.
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return MVT::i32;
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}
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TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
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const override {
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// Widen subvectors to the full width rather than promoting integer
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// elements. This is better because:
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//
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// (a) it means that we can handle the ABI for passing and returning
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// sub-128 vectors without having to handle them as legal types.
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//
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// (b) we don't have instructions to extend on load and truncate on store,
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// so promoting the integers is less efficient.
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//
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// (c) there are no multiplication instructions for the widest integer
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// type (v2i64).
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if (VT.getVectorElementType().getSizeInBits() % 8 == 0)
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return TypeWidenVector;
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return TargetLoweringBase::getPreferredVectorAction(VT);
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}
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
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EVT) const override;
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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bool isLegalICmpImmediate(int64_t Imm) const override;
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bool isLegalAddImmediate(int64_t Imm) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS) const override;
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bool isFoldableMemAccessOffset(Instruction *I, int64_t Offset) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
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unsigned Align,
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bool *Fast) const override;
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bool isTruncateFree(Type *, Type *) const override;
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bool isTruncateFree(EVT, EVT) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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TargetLowering::ConstraintType
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getConstraintType(StringRef Constraint) const override;
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TargetLowering::ConstraintWeight
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getSingleConstraintMatchWeight(AsmOperandInfo &info,
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const char *constraint) const override;
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void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode.size() == 1) {
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switch(ConstraintCode[0]) {
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default:
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break;
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case 'Q':
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return InlineAsm::Constraint_Q;
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case 'R':
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return InlineAsm::Constraint_R;
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case 'S':
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return InlineAsm::Constraint_S;
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case 'T':
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return InlineAsm::Constraint_T;
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}
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}
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return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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}
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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unsigned
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getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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return SystemZ::R6D;
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}
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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unsigned
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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return SystemZ::R7D;
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}
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/// Override to support customized stack guard loading.
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bool useLoadStackGuardNode() const override {
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return true;
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}
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void insertSSPDeclarations(Module &M) const override {
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}
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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bool allowTruncateForTailCall(Type *, Type *) const override;
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bool mayBeEmittedAsTailCall(CallInst *CI) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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ISD::NodeType getExtendForAtomicOps() const override {
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return ISD::ANY_EXTEND;
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}
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bool supportSwiftError() const override {
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return true;
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}
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private:
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const SystemZSubtarget &Subtarget;
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// Implement LowerOperation for individual opcodes.
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SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
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SelectionDAG &DAG, unsigned Opcode,
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|
SDValue GOTOffset) const;
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SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(BlockAddressSDNode *Node,
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SelectionDAG &DAG) const;
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SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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|
SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
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|
SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
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|
SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
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|
unsigned Opcode) const;
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|
SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
|
|
SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
|
|
unsigned UnpackHigh) const;
|
|
SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
|
|
|
|
SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
|
|
unsigned Index, DAGCombinerInfo &DCI,
|
|
bool Force) const;
|
|
SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
|
|
DAGCombinerInfo &DCI) const;
|
|
SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
SDValue combineSHIFTROT(SDNode *N, DAGCombinerInfo &DCI) const;
|
|
|
|
// If the last instruction before MBBI in MBB was some form of COMPARE,
|
|
// try to replace it with a COMPARE AND BRANCH just before MBBI.
|
|
// CCMask and Target are the BRC-like operands for the branch.
|
|
// Return true if the change was made.
|
|
bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
unsigned CCMask,
|
|
MachineBasicBlock *Target) const;
|
|
|
|
// Implement EmitInstrWithCustomInserter for individual operation types.
|
|
MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
|
|
MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
|
|
unsigned StoreOpcode, unsigned STOCOpcode,
|
|
bool Invert) const;
|
|
MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
|
|
bool ClearEven, unsigned SubReg) const;
|
|
MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
|
|
MachineBasicBlock *BB,
|
|
unsigned BinOpcode, unsigned BitSize,
|
|
bool Invert = false) const;
|
|
MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned CompareOpcode,
|
|
unsigned KeepOldMask,
|
|
unsigned BitSize) const;
|
|
MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const;
|
|
MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
|
|
unsigned Opcode) const;
|
|
MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
|
|
unsigned Opcode) const;
|
|
MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned Opcode, bool NoFloat) const;
|
|
MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
|
|
MachineBasicBlock *MBB,
|
|
unsigned Opcode) const;
|
|
};
|
|
} // end namespace llvm
|
|
|
|
#endif
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