85 lines
2.8 KiB
C++
85 lines
2.8 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the InstructionSelector class.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#define DEBUG_TYPE "instructionselector"
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using namespace llvm;
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InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
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: Renderers(MaxRenderers), MIs() {}
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InstructionSelector::InstructionSelector() = default;
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bool InstructionSelector::constrainOperandRegToRegClass(
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MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
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const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const {
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MachineBasicBlock &MBB = *I.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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return
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constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
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}
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bool InstructionSelector::isOperandImmEqual(
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const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const {
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if (MO.isReg() && MO.getReg())
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if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
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return *VRegVal == Value;
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return false;
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}
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bool InstructionSelector::isBaseWithConstantOffset(
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const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
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if (!Root.isReg())
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return false;
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MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
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if (RootI->getOpcode() != TargetOpcode::G_GEP)
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return false;
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MachineOperand &RHS = RootI->getOperand(2);
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MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
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if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
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return false;
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return true;
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}
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bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
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MachineInstr &IntoMI) const {
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// Immediate neighbours are already folded.
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if (MI.getParent() == IntoMI.getParent() &&
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std::next(MI.getIterator()) == IntoMI.getIterator())
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return true;
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return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
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MI.implicit_operands().begin() == MI.implicit_operands().end();
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}
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