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llvm-project/llvm/lib/Target/AArch64
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Diogo N. Sampaio 352a2fa1e7 [AARCH64][FIX] Emit data symbol for constant pool data 
The ARM64 elf emitter would omit printing data
symbol for zero filled constant data. This patch
overrides the emitFill method as to enforce that
the symbol is correctly printed.

Differential revision: https://reviews.llvm.org/D53132

llvm-svn: 344248
 		2018-10-11 14:10:32 +00:00
..
AsmParser [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
Disassembler [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
InstPrinter [AArch64][v8.5A] Add Branch Target Identification instructions 2018-09-27 14:54:33 +00:00
MCTargetDesc [AARCH64][FIX] Emit data symbol for constant pool data 2018-10-11 14:10:32 +00:00
TargetInfo
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Utils [AArch64][v8.5A] Add Branch Target Identification instructions 2018-09-27 14:54:33 +00:00
AArch64.h [AArch64][v8.5A] Branch Target Identification code-generation pass 2018-10-08 14:04:24 +00:00
AArch64.td [AArch64][v8.5A] Add MTE as an optional AArch64 extension 2018-10-02 09:36:28 +00:00
AArch64A53Fix835769.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64A57FPLoadBalancing.cpp llvm::sort(C.begin(), C.end(), ...) -> llvm::sort(C, ...) 2018-09-27 02:13:45 +00:00
AArch64AdvSIMDScalarPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64AsmPrinter.cpp [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI 2018-10-08 14:09:15 +00:00
AArch64BranchTargets.cpp [AArch64][v8.5A] Branch Target Identification code-generation pass 2018-10-08 14:04:24 +00:00
AArch64CallLowering.cpp [AArch64] Support adding X[8-15,18] registers as CSRs. 2018-09-22 22:17:50 +00:00
AArch64CallLowering.h [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value 2018-08-02 08:33:31 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td [AArch64] Implement aarch64_vector_pcs codegen support. 2018-09-12 12:10:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64CondBrTuning.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionOptimizer.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ConditionalCompares.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64DeadRegisterDefinitionsPass.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
AArch64FalkorHWPFFix.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64FastISel.cpp [AArch64] Support adding X[8-15,18] registers as CSRs. 2018-09-22 22:17:50 +00:00
AArch64FrameLowering.cpp [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI 2018-10-08 14:09:15 +00:00
AArch64FrameLowering.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [AArch64][v8.5A] Add speculation restriction system registers 2018-09-27 14:05:46 +00:00
AArch64ISelLowering.cpp [AArch64] Share search bookkeeping in combines. NFCI. 2018-09-25 15:30:22 +00:00
AArch64ISelLowering.h [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR 2018-09-19 14:51:42 +00:00
AArch64InstrAtomics.td [AArch64] Improve v8.1-A code-gen for atomic load-and 2018-02-12 17:03:11 +00:00
AArch64InstrFormats.td [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
AArch64InstrInfo.cpp [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled 2018-10-08 14:12:08 +00:00
AArch64InstrInfo.h [MachineOutliner][AArch64] Add support for saving LR to a register 2018-07-30 17:45:28 +00:00
AArch64InstrInfo.td [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI 2018-10-08 14:09:15 +00:00
AArch64InstructionSelector.cpp [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
AArch64LegalizerInfo.cpp [AArch64][GlobalISel] Make G_BLOCK_ADDR legal. 2018-07-31 00:08:56 +00:00
AArch64LegalizerInfo.h
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AArch64LoadStoreOptimizer.cpp [MI] Change the array of `MachineMemOperand` pointers to be 2018-08-16 21:30:05 +00:00
AArch64MCInstLower.cpp [MinGW] [AArch64] Add stubs for potential automatic dllimported variables 2018-09-04 20:56:21 +00:00
AArch64MCInstLower.h
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AArch64MachineFunctionInfo.h Remove trailing space 2018-07-30 19:41:25 +00:00
AArch64MacroFusion.cpp AArch64: Add FuseCryptoEOR fusion rules 2018-09-19 20:50:51 +00:00
AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PreLegalizerCombiner.cpp Add the missing new files from r343654 2018-10-03 02:21:30 +00:00
AArch64PromoteConstant.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64RedundantCopyElimination.cpp [CodeGen][AArch64] Use RegUnits to track register aliases. (NFC) 2018-05-23 17:49:38 +00:00
AArch64RegisterBankInfo.cpp
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AArch64RegisterBankInfo.h
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [Aarch64] Fix memcpy that was copying 4x too many bytes 2018-09-23 18:43:28 +00:00
AArch64RegisterInfo.h [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() 2018-10-05 14:23:11 +00:00
AArch64RegisterInfo.td [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI 2018-10-08 14:09:15 +00:00
AArch64SIMDInstrOpt.cpp [TargetSchedule] shrink interface for init(); NFCI 2018-04-08 19:56:04 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Enable instructions to be prefixed. 2018-07-30 16:05:45 +00:00
AArch64SchedA53.td [AArch64] Clean-up a few over-eager regexps in models. 2018-03-23 11:00:42 +00:00
AArch64SchedA57.td
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AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td
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AArch64SchedExynosM1.td [ExynosM1][Sched] Fix resource usage in scheduling model. 2018-06-11 07:33:08 +00:00
AArch64SchedExynosM3.td [ExynosM3] Fix scheduling info. 2018-05-18 13:10:41 +00:00
AArch64SchedFalkor.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Correct load/store increment scheduling details 2018-03-20 13:46:35 +00:00
AArch64SchedKryo.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedKryoDetails.td
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AArch64SchedThunderX.td [TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. 2018-03-18 19:56:15 +00:00
AArch64SchedThunderX2T99.td [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles. 2018-06-13 09:41:49 +00:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp AArch64/X86: Factor out common bzero logic; NFC 2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
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AArch64StorePairSuppress.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
AArch64Subtarget.cpp [AArch64] Support adding X[8-15,18] registers as CSRs. 2018-09-22 22:17:50 +00:00
AArch64Subtarget.h [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
AArch64SystemOperands.td [AArch64][v8.5A] Add Memory Tagging system registers 2018-10-02 09:54:35 +00:00
AArch64TargetMachine.cpp [AArch64][v8.5A] Branch Target Identification code-generation pass 2018-10-08 14:04:24 +00:00
AArch64TargetMachine.h (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp [AArch64] DWARF: do not generate AT_location for thread local 2018-08-01 23:46:49 +00:00
AArch64TargetObjectFile.h Move TargetLoweringObjectFile from CodeGen to Target to fix layering 2018-03-23 23:58:19 +00:00
AArch64TargetTransformInfo.cpp Remove trailing space 2018-07-30 19:41:25 +00:00
AArch64TargetTransformInfo.h [TTI, AArch64] Add transpose shuffle kind 2018-04-26 13:48:33 +00:00
CMakeLists.txt [AArch64][v8.5A] Branch Target Identification code-generation pass 2018-10-08 14:04:24 +00:00
LLVMBuild.txt
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SVEInstrFormats.td Remove extra whitespace. NFC. (test commit) 2018-09-28 08:45:28 +00:00