104 lines
2.9 KiB
C++
104 lines
2.9 KiB
C++
//===- ARCExpandPseudosPass - ARC expand pseudo loads -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass expands stores with large offsets into an appropriate sequence.
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//===----------------------------------------------------------------------===//
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#include "ARC.h"
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#include "ARCInstrInfo.h"
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#include "ARCRegisterInfo.h"
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#include "ARCSubtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "arc-expand-pseudos"
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namespace {
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class ARCExpandPseudos : public MachineFunctionPass {
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public:
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static char ID;
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ARCExpandPseudos() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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StringRef getPassName() const override { return "ARC Expand Pseudos"; }
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private:
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void ExpandStore(MachineFunction &, MachineBasicBlock::iterator);
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const ARCInstrInfo *TII;
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};
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char ARCExpandPseudos::ID = 0;
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} // end anonymous namespace
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static unsigned getMappedOp(unsigned PseudoOp) {
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switch (PseudoOp) {
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case ARC::ST_FAR:
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return ARC::ST_rs9;
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case ARC::STH_FAR:
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return ARC::STH_rs9;
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case ARC::STB_FAR:
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return ARC::STB_rs9;
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default:
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llvm_unreachable("Unhandled pseudo op.");
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}
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}
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void ARCExpandPseudos::ExpandStore(MachineFunction &MF,
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MachineBasicBlock::iterator SII) {
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MachineInstr &SI = *SII;
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unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass);
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unsigned AddOpc =
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isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
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BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
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.addReg(SI.getOperand(1).getReg())
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.addImm(SI.getOperand(2).getImm());
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BuildMI(*SI.getParent(), SI, SI.getDebugLoc(),
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TII->get(getMappedOp(SI.getOpcode())))
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.addReg(SI.getOperand(0).getReg())
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.addReg(AddrReg)
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.addImm(0);
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SI.eraseFromParent();
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}
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bool ARCExpandPseudos::runOnMachineFunction(MachineFunction &MF) {
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const ARCSubtarget *STI = &MF.getSubtarget<ARCSubtarget>();
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TII = STI->getInstrInfo();
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bool ExpandedStore = false;
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for (auto &MBB : MF) {
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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switch (MBBI->getOpcode()) {
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case ARC::ST_FAR:
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case ARC::STH_FAR:
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case ARC::STB_FAR:
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ExpandStore(MF, MBBI);
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ExpandedStore = true;
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break;
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default:
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break;
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}
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MBBI = NMBBI;
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}
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}
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return ExpandedStore;
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}
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FunctionPass *llvm::createARCExpandPseudosPass() {
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return new ARCExpandPseudos();
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}
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