234 lines
10 KiB
TableGen
234 lines
10 KiB
TableGen
//===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'A', Atomic
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// Instructions extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs1),
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opcodestr, "$rd, (${rs1})"> {
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let rs2 = 0;
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}
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multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
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def "" : LR_r<0, 0, funct3, opcodestr>;
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def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
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def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
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class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs2, (${rs1})">;
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multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
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def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
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def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
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def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
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}
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multiclass AtomicStPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> {
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def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>;
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def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>;
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def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2),
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(Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>;
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def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
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(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
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def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2),
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(Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtA] in {
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defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
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defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
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defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
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defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
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defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
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defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
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defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
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defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
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defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
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defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
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defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
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} // Predicates = [HasStdExtA]
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let Predicates = [HasStdExtA, IsRV64] in {
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defm LR_D : LR_r_aq_rl<0b011, "lr.d">;
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defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
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defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
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defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
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defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
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defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
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defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
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defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
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defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
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} // Predicates = [HasStedExtA, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtA] in {
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/// Atomic loads and stores
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// Fences will be inserted for atomic load/stores according to the logic in
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// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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defm : LdPat<atomic_load_8, LB>;
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defm : LdPat<atomic_load_16, LH>;
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defm : LdPat<atomic_load_32, LW>;
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defm : AtomicStPat<atomic_store_8, SB, GPR>;
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defm : AtomicStPat<atomic_store_16, SH, GPR>;
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defm : AtomicStPat<atomic_store_32, SW, GPR>;
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/// AMOs
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multiclass AMOPat<string AtomicOp, string BaseInst> {
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
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!cast<RVInst>(BaseInst)>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
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!cast<RVInst>(BaseInst#"_AQ")>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"),
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!cast<RVInst>(BaseInst#"_RL")>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
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!cast<RVInst>(BaseInst#"_AQ_RL")>;
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def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
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!cast<RVInst>(BaseInst#"_AQ_RL")>;
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}
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defm : AMOPat<"atomic_swap_32", "AMOSWAP_W">;
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defm : AMOPat<"atomic_load_add_32", "AMOADD_W">;
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defm : AMOPat<"atomic_load_and_32", "AMOAND_W">;
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defm : AMOPat<"atomic_load_or_32", "AMOOR_W">;
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defm : AMOPat<"atomic_load_xor_32", "AMOXOR_W">;
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defm : AMOPat<"atomic_load_max_32", "AMOMAX_W">;
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defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">;
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defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">;
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defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">;
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def : Pat<(atomic_load_sub_32_monotonic GPR:$addr, GPR:$incr),
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(AMOADD_W GPR:$addr, (SUB X0, GPR:$incr))>;
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def : Pat<(atomic_load_sub_32_acquire GPR:$addr, GPR:$incr),
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(AMOADD_W_AQ GPR:$addr, (SUB X0, GPR:$incr))>;
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def : Pat<(atomic_load_sub_32_release GPR:$addr, GPR:$incr),
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(AMOADD_W_RL GPR:$addr, (SUB X0, GPR:$incr))>;
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def : Pat<(atomic_load_sub_32_acq_rel GPR:$addr, GPR:$incr),
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(AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
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def : Pat<(atomic_load_sub_32_seq_cst GPR:$addr, GPR:$incr),
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(AMOADD_W_AQ_RL GPR:$addr, (SUB X0, GPR:$incr))>;
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/// Pseudo AMOs
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class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$incr, ixlenimm:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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def PseudoAtomicLoadNand32 : PseudoAMO;
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// Ordering constants must be kept in sync with the AtomicOrdering enum in
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// AtomicOrdering.h.
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def : Pat<(atomic_load_nand_32_monotonic GPR:$addr, GPR:$incr),
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(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 2)>;
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def : Pat<(atomic_load_nand_32_acquire GPR:$addr, GPR:$incr),
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(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 4)>;
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def : Pat<(atomic_load_nand_32_release GPR:$addr, GPR:$incr),
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(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 5)>;
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def : Pat<(atomic_load_nand_32_acq_rel GPR:$addr, GPR:$incr),
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(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 6)>;
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def : Pat<(atomic_load_nand_32_seq_cst GPR:$addr, GPR:$incr),
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(PseudoAtomicLoadNand32 GPR:$addr, GPR:$incr, 7)>;
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class PseudoMaskedAMO
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: Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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class PseudoMaskedAMOMinMax
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: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$sextshamt,
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ixlenimm:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
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"@earlyclobber $scratch2";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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class PseudoMaskedAMOUMinUMax
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: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
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"@earlyclobber $scratch2";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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class PseudoMaskedAMOPat<Intrinsic intrin, Pseudo AMOInst>
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: Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, imm:$ordering),
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, imm:$ordering)>;
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class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
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: Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
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imm:$ordering),
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
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imm:$ordering)>;
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def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i32,
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PseudoMaskedAtomicSwap32>;
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def PseudoMaskedAtomicLoadAdd32 : PseudoMaskedAMO;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add_i32,
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PseudoMaskedAtomicLoadAdd32>;
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def PseudoMaskedAtomicLoadSub32 : PseudoMaskedAMO;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub_i32,
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PseudoMaskedAtomicLoadSub32>;
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def PseudoMaskedAtomicLoadNand32 : PseudoMaskedAMO;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand_i32,
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PseudoMaskedAtomicLoadNand32>;
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def PseudoMaskedAtomicLoadMax32 : PseudoMaskedAMOMinMax;
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def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max_i32,
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PseudoMaskedAtomicLoadMax32>;
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def PseudoMaskedAtomicLoadMin32 : PseudoMaskedAMOMinMax;
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def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min_i32,
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PseudoMaskedAtomicLoadMin32>;
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def PseudoMaskedAtomicLoadUMax32 : PseudoMaskedAMOUMinUMax;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax_i32,
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PseudoMaskedAtomicLoadUMax32>;
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def PseudoMaskedAtomicLoadUMin32 : PseudoMaskedAMOUMinUMax;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i32,
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PseudoMaskedAtomicLoadUMin32>;
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} // Predicates = [HasStdExtA]
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