52 lines
2.0 KiB
TableGen
52 lines
2.0 KiB
TableGen
//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'M', Integer
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// Multiplication and Division instruction set extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtM] in {
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def MUL : ALU_rr<0b0000001, 0b000, "mul">;
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def MULH : ALU_rr<0b0000001, 0b001, "mulh">;
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def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
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def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
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def DIV : ALU_rr<0b0000001, 0b100, "div">;
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def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
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def REM : ALU_rr<0b0000001, 0b110, "rem">;
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def REMU : ALU_rr<0b0000001, 0b111, "remu">;
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} // Predicates = [HasStdExtM]
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let Predicates = [HasStdExtM, IsRV64] in {
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def MULW : ALUW_rr<0b0000001, 0b000, "mulw">;
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def DIVW : ALUW_rr<0b0000001, 0b100, "divw">;
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def DIVUW : ALUW_rr<0b0000001, 0b101, "divuw">;
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def REMW : ALUW_rr<0b0000001, 0b110, "remw">;
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def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">;
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} // Predicates = [HasStdExtM, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtM] in {
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def : PatGprGpr<mul, MUL>;
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def : PatGprGpr<mulhs, MULH>;
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def : PatGprGpr<mulhu, MULHU>;
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// No ISDOpcode for mulhsu
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def : PatGprGpr<sdiv, DIV>;
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def : PatGprGpr<udiv, DIVU>;
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def : PatGprGpr<srem, REM>;
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def : PatGprGpr<urem, REMU>;
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} // Predicates = [HasStdExtM]
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