234 lines
8.4 KiB
C++
234 lines
8.4 KiB
C++
//===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SparcMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/SparcFixupKinds.h"
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#include "SparcMCExpr.h"
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#include "SparcMCTargetDesc.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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class SparcMCCodeEmitter : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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public:
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SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
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: MCII(mcii), Ctx(ctx) {}
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SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
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SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
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~SparcMCCodeEmitter() override = default;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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private:
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uint64_t computeAvailableFeatures(const FeatureBitset &FB) const;
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void verifyInstructionPredicates(const MCInst &MI,
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uint64_t AvailableFeatures) const;
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};
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} // end anonymous namespace
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void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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verifyInstructionPredicates(MI,
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computeAvailableFeatures(STI.getFeatureBits()));
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unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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support::endian::write(OS, Bits,
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Ctx.getAsmInfo()->isLittleEndian() ? support::little
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: support::big);
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unsigned tlsOpNo = 0;
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switch (MI.getOpcode()) {
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default: break;
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case SP::TLS_CALL: tlsOpNo = 1; break;
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case SP::TLS_ADDrr:
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case SP::TLS_ADDXrr:
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case SP::TLS_LDrr:
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case SP::TLS_LDXrr: tlsOpNo = 3; break;
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}
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if (tlsOpNo != 0) {
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const MCOperand &MO = MI.getOperand(tlsOpNo);
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uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
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assert(op == 0 && "Unexpected operand value!");
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(void)op; // suppress warning.
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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unsigned SparcMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr());
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const MCExpr *Expr = MO.getExpr();
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if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
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MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
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Fixups.push_back(MCFixup::create(0, Expr, Kind));
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return 0;
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}
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int64_t Res;
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if (Expr->evaluateAsAbsolute(Res))
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return Res;
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llvm_unreachable("Unhandled expression!");
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return 0;
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}
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unsigned SparcMCCodeEmitter::
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getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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if (MI.getOpcode() == SP::TLS_CALL) {
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// No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
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// encodeInstruction.
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#ifndef NDEBUG
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// Verify that the callee is actually __tls_get_addr.
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const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr());
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assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
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"Unexpected expression in TLS_CALL");
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const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
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assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
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"Unexpected function for TLS_CALL");
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#endif
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return 0;
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}
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MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30;
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if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
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if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
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fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30;
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}
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind));
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return 0;
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}
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unsigned SparcMCCodeEmitter::
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getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)Sparc::fixup_sparc_br22));
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return 0;
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}
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unsigned SparcMCCodeEmitter::
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getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)Sparc::fixup_sparc_br19));
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return 0;
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}
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unsigned SparcMCCodeEmitter::
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getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)Sparc::fixup_sparc_br16_2));
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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(MCFixupKind)Sparc::fixup_sparc_br16_14));
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return 0;
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}
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#define ENABLE_INSTR_PREDICATE_VERIFIER
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#include "SparcGenMCCodeEmitter.inc"
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MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new SparcMCCodeEmitter(MCII, Ctx);
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}
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