387 lines
14 KiB
C++
387 lines
14 KiB
C++
//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcFrameLowering.h"
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#include "SparcInstrInfo.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableLeafProc("disable-sparc-leaf-proc",
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cl::init(false),
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cl::desc("Disable Sparc leaf procedure optimization."),
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cl::Hidden);
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SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
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ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
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void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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int NumBytes,
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unsigned ADDrr,
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unsigned ADDri) const {
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DebugLoc dl;
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
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if (NumBytes >= -4096 && NumBytes < 4096) {
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BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
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.addReg(SP::O6).addImm(NumBytes);
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return;
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}
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// Emit this the hard way. This clobbers G1 which we always know is
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// available here.
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if (NumBytes >= 0) {
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// Emit nonnegative numbers with sethi + or.
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// sethi %hi(NumBytes), %g1
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// or %g1, %lo(NumBytes), %g1
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// add %sp, %g1, %sp
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HI22(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
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.addReg(SP::G1).addImm(LO10(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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return ;
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}
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// Emit negative numbers with sethi + xor.
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// sethi %hix(NumBytes), %g1
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// xor %g1, %lox(NumBytes), %g1
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// add %sp, %g1, %sp
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HIX22(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
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.addReg(SP::G1).addImm(LOX10(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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}
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void SparcFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineFrameInfo &MFI = MF.getFrameInfo();
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
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const SparcRegisterInfo &RegInfo =
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*static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc dl;
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bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
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// FIXME: unfortunately, returning false from canRealignStack
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// actually just causes needsStackRealignment to return false,
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// rather than reporting an error, as would be sensible. This is
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// poor, but fixing that bogosity is going to be a large project.
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// For now, just see if it's lied, and report an error here.
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if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())
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report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
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"stack re-alignment, but LLVM couldn't handle it "
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"(probably because it has a dynamic alloca).");
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI.getStackSize();
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unsigned SAVEri = SP::SAVEri;
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unsigned SAVErr = SP::SAVErr;
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if (FuncInfo->isLeafProc()) {
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if (NumBytes == 0)
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return;
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SAVEri = SP::ADDri;
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SAVErr = SP::ADDrr;
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}
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// The SPARC ABI is a bit odd in that it requires a reserved 92-byte
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// (128 in v9) area in the user's stack, starting at %sp. Thus, the
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// first part of the stack that can actually be used is located at
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// %sp + 92.
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//
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// We therefore need to add that offset to the total stack size
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// after all the stack objects are placed by
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// PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
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// aligned *after* the extra size is added, we need to disable
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// calculateFrameObjectOffsets's built-in stack alignment, by having
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// targetHandlesStackFrameRounding return true.
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// Add the extra call frame stack size, if needed. (This is the same
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// code as in PrologEpilogInserter, but also gets disabled by
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// targetHandlesStackFrameRounding)
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if (MFI.adjustsStack() && hasReservedCallFrame(MF))
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NumBytes += MFI.getMaxCallFrameSize();
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// Adds the SPARC subtarget-specific spill area to the stack
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// size. Also ensures target-required alignment.
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NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
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// Finally, ensure that the size is sufficiently aligned for the
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// data on the stack.
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if (MFI.getMaxAlignment() > 0) {
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NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
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}
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// Update stack size with corrected value.
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MFI.setStackSize(NumBytes);
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emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
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unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
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// Emit ".cfi_def_cfa_register 30".
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unsigned CFIIndex =
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MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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// Emit ".cfi_window_save".
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CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
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unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
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// Emit ".cfi_register 15, 31".
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CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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if (NeedsStackRealignment) {
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int64_t Bias = Subtarget.getStackPointerBias();
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unsigned regUnbiased;
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if (Bias) {
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// This clobbers G1 which we always know is available here.
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regUnbiased = SP::G1;
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// add %o6, BIAS, %g1
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BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
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.addReg(SP::O6).addImm(Bias);
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} else
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regUnbiased = SP::O6;
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// andn %regUnbiased, MaxAlign-1, %regUnbiased
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int MaxAlign = MFI.getMaxAlignment();
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BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
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.addReg(regUnbiased).addImm(MaxAlign - 1);
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if (Bias) {
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// add %g1, -BIAS, %o6
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BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
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.addReg(regUnbiased).addImm(-Bias);
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}
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}
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}
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MachineBasicBlock::iterator SparcFrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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MachineInstr &MI = *I;
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int Size = MI.getOperand(0).getImm();
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
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}
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return MBB.erase(I);
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}
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void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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assert(MBBI->getOpcode() == SP::RETL &&
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"Can only put epilog before 'retl' instruction!");
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if (!FuncInfo->isLeafProc()) {
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BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
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.addReg(SP::G0);
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return;
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}
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MachineFrameInfo &MFI = MF.getFrameInfo();
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int NumBytes = (int) MFI.getStackSize();
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if (NumBytes == 0)
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return;
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emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
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}
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bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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// Reserve call frame if there are no variable sized objects on the stack.
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return !MF.getFrameInfo().hasVarSizedObjects();
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
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const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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RegInfo->needsStackRealignment(MF) ||
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MFI.hasVarSizedObjects() ||
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MFI.isFrameAddressTaken();
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}
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int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const {
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
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const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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bool isFixed = MFI.isFixedObjectIndex(FI);
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// Addressable stack objects are accessed using neg. offsets from
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// %fp, or positive offsets from %sp.
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bool UseFP;
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// Sparc uses FP-based references in general, even when "hasFP" is
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// false. That function is rather a misnomer, because %fp is
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// actually always available, unless isLeafProc.
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if (FuncInfo->isLeafProc()) {
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// If there's a leaf proc, all offsets need to be %sp-based,
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// because we haven't caused %fp to actually point to our frame.
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UseFP = false;
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} else if (isFixed) {
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// Otherwise, argument access should always use %fp.
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UseFP = true;
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} else if (RegInfo->needsStackRealignment(MF)) {
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// If there is dynamic stack realignment, all local object
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// references need to be via %sp, to take account of the
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// re-alignment.
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UseFP = false;
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} else {
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// Finally, default to using %fp.
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UseFP = true;
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}
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int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
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Subtarget.getStackPointerBias();
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if (UseFP) {
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FrameReg = RegInfo->getFrameRegister(MF);
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return FrameOffset;
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} else {
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FrameReg = SP::O6; // %sp
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return FrameOffset + MF.getFrameInfo().getStackSize();
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}
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}
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static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
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{
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
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if (MRI->isPhysRegUsed(reg))
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return false;
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for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
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if (MRI->isPhysRegUsed(reg))
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return false;
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return true;
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}
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bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
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{
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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return !(MFI.hasCalls() // has calls
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|| MRI.isPhysRegUsed(SP::L0) // Too many registers needed
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|| MRI.isPhysRegUsed(SP::O6) // %sp is used
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|| hasFP(MF)); // need %fp
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}
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void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Remap %i[0-7] to %o[0-7].
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
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if (!MRI.isPhysRegUsed(reg))
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continue;
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unsigned mapped_reg = reg - SP::I0 + SP::O0;
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// Replace I register with O register.
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MRI.replaceRegWith(reg, mapped_reg);
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// Also replace register pair super-registers.
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if ((reg - SP::I0) % 2 == 0) {
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unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
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unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
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MRI.replaceRegWith(preg, mapped_preg);
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}
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}
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// Rewrite MBB's Live-ins.
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
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if (!MBB->isLiveIn(reg))
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continue;
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MBB->removeLiveIn(reg);
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MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
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}
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
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if (!MBB->isLiveIn(reg))
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continue;
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MBB->removeLiveIn(reg);
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MBB->addLiveIn(reg - SP::I0 + SP::O0);
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}
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}
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assert(verifyLeafProcRegUse(&MRI));
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#ifdef EXPENSIVE_CHECKS
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MF.verify(0, "After LeafProc Remapping");
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#endif
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}
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void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
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BitVector &SavedRegs,
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RegScavenger *RS) const {
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TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
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if (!DisableLeafProc && isLeafProc(MF)) {
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SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
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MFI->setLeafProc(true);
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remapRegsForLeafProc(MF);
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}
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}
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