143 lines
4.6 KiB
C++
143 lines
4.6 KiB
C++
//===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes common code for rendering MCInst instances as Intel-style
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// and Intel-style assembly.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstPrinterCommon.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/Casting.h"
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#include <cstdint>
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#include <cassert>
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using namespace llvm;
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void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid ssecc/avxcc argument!");
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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case 8: O << "eq_uq"; break;
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case 9: O << "nge"; break;
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case 0xa: O << "ngt"; break;
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case 0xb: O << "false"; break;
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case 0xc: O << "neq_oq"; break;
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case 0xd: O << "ge"; break;
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case 0xe: O << "gt"; break;
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case 0xf: O << "true"; break;
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case 0x10: O << "eq_os"; break;
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case 0x11: O << "lt_oq"; break;
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case 0x12: O << "le_oq"; break;
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case 0x13: O << "unord_s"; break;
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case 0x14: O << "neq_us"; break;
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case 0x15: O << "nlt_uq"; break;
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case 0x16: O << "nle_uq"; break;
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case 0x17: O << "ord_s"; break;
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case 0x18: O << "eq_us"; break;
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case 0x19: O << "nge_uq"; break;
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case 0x1a: O << "ngt_uq"; break;
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case 0x1b: O << "false_os"; break;
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case 0x1c: O << "neq_os"; break;
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case 0x1d: O << "ge_oq"; break;
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case 0x1e: O << "gt_oq"; break;
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case 0x1f: O << "true_us"; break;
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}
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}
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void X86InstPrinterCommon::printXOPCC(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm();
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switch (Imm) {
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default: llvm_unreachable("Invalid xopcc argument!");
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case 0: O << "lt"; break;
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case 1: O << "le"; break;
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case 2: O << "gt"; break;
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case 3: O << "ge"; break;
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case 4: O << "eq"; break;
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case 5: O << "neq"; break;
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case 6: O << "false"; break;
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case 7: O << "true"; break;
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}
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}
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void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
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switch (Imm) {
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case 0: O << "{rn-sae}"; break;
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case 1: O << "{rd-sae}"; break;
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case 2: O << "{ru-sae}"; break;
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case 3: O << "{rz-sae}"; break;
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}
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}
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/// printPCRelImm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value (e.g. for jumps and calls). In
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/// Intel-style these print slightly differently than normal immediates.
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/// for example, a $ is not emitted.
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void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm())
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O << formatImm(Op.getImm());
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else {
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assert(Op.isExpr() && "unknown pcrel immediate operand");
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// If a symbolic branch target was added as a constant expression then print
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// that address in hex.
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const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
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int64_t Address;
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if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
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O << formatHex((uint64_t)Address);
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} else {
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// Otherwise, just print the expression.
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Op.getExpr()->print(O, &MAI);
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}
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}
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}
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void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getReg()) {
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printOperand(MI, OpNo, O);
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O << ':';
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}
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}
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void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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uint64_t TSFlags = Desc.TSFlags;
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unsigned Flags = MI->getFlags();
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if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
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O << "\tlock\t";
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if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK))
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O << "\tnotrack\t";
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if (Flags & X86::IP_HAS_REPEAT_NE)
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O << "\trepne\t";
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else if (Flags & X86::IP_HAS_REPEAT)
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O << "\trep\t";
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}
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