142 lines
3.3 KiB
LLVM
142 lines
3.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
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; Test efficient codegen of vector extends up from legal type to 128 bit
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; and 256 bit vector types.
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;-----
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; Vectors of i16.
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;-----
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define <8 x i16> @func1(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: func1:
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <8 x i8> %v0 to <8 x i16>
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ret <8 x i16> %r
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}
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define <8 x i16> @func2(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: func2:
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <8 x i8> %v0 to <8 x i16>
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ret <8 x i16> %r
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}
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define <16 x i16> @func3(<16 x i8> %v0) nounwind {
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; CHECK-LABEL: func3:
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; CHECK-NEXT: ushll2.8h v1, v0, #0
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <16 x i8> %v0 to <16 x i16>
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ret <16 x i16> %r
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}
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define <16 x i16> @func4(<16 x i8> %v0) nounwind {
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; CHECK-LABEL: func4:
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; CHECK-NEXT: sshll2.8h v1, v0, #0
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <16 x i8> %v0 to <16 x i16>
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ret <16 x i16> %r
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}
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;-----
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; Vectors of i32.
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;-----
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define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc1:
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <4 x i16> %v0 to <4 x i32>
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ret <4 x i32> %r
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}
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define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc2:
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <4 x i16> %v0 to <4 x i32>
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ret <4 x i32> %r
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}
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define <8 x i32> @afunc3(<8 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc3:
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; CHECK-NEXT: ushll2.4s v1, v0, #0
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <8 x i16> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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define <8 x i32> @afunc4(<8 x i16> %v0) nounwind {
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; CHECK-LABEL: afunc4:
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; CHECK-NEXT: sshll2.4s v1, v0, #0
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <8 x i16> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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define <8 x i32> @bfunc1(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: bfunc1:
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; CHECK-NEXT: ushll.8h v0, v0, #0
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; CHECK-NEXT: ushll2.4s v1, v0, #0
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <8 x i8> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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define <8 x i32> @bfunc2(<8 x i8> %v0) nounwind {
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; CHECK-LABEL: bfunc2:
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; CHECK-NEXT: sshll.8h v0, v0, #0
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; CHECK-NEXT: sshll2.4s v1, v0, #0
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <8 x i8> %v0 to <8 x i32>
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ret <8 x i32> %r
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}
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;-----
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; Vectors of i64.
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;-----
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define <4 x i64> @zfunc1(<4 x i32> %v0) nounwind {
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; CHECK-LABEL: zfunc1:
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <4 x i32> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @zfunc2(<4 x i32> %v0) nounwind {
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; CHECK-LABEL: zfunc2:
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; CHECK-NEXT: sshll2.2d v1, v0, #0
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; CHECK-NEXT: sshll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <4 x i32> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @bfunc3(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: func3:
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; CHECK-NEXT: ushll.4s v0, v0, #0
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = zext <4 x i16> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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define <4 x i64> @cfunc4(<4 x i16> %v0) nounwind {
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; CHECK-LABEL: func4:
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; CHECK-NEXT: sshll.4s v0, v0, #0
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; CHECK-NEXT: sshll2.2d v1, v0, #0
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; CHECK-NEXT: sshll.2d v0, v0, #0
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; CHECK-NEXT: ret
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%r = sext <4 x i16> %v0 to <4 x i64>
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ret <4 x i64> %r
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}
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