164 lines
5.5 KiB
LLVM
164 lines
5.5 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
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@in = global float 0x400921FA00000000, align 4
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@iin = global i32 -1023, align 4
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@uin = global i32 1023, align 4
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declare void @foo_int32x4_t(<4 x i32>)
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; Test signed conversion.
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; CHECK: t1
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; CHECK-NOT: {{vdiv|vmul}}
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define void @t1() nounwind {
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entry:
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%tmp = load i32, i32* @iin, align 4
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%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
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%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
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%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
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tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
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ret void
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}
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declare void @foo_float32x2_t(<2 x float>)
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; Test unsigned conversion.
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; CHECK: t2
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; CHECK-NOT: {{vdiv|vmul}}
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define void @t2() nounwind {
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entry:
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%tmp = load i32, i32* @uin, align 4
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%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
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%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
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%vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
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tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
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ret void
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}
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; Test which should not fold due to non-power of 2.
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; CHECK: t3
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; CHECK: {{vdiv|vmul}}
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define void @t3() nounwind {
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entry:
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%tmp = load i32, i32* @iin, align 4
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%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
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%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
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%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 0x401B333340000000, float 0x401B333340000000>
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tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
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ret void
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}
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; Test which should not fold due to power of 2 out of range.
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; CHECK: t4
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; CHECK: {{vdiv|vmul}}
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define void @t4() nounwind {
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entry:
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%tmp = load i32, i32* @iin, align 4
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%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
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%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
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%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
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tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
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ret void
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}
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; Test case where const is max power of 2 (i.e., 2^32).
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; CHECK: t5
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; CHECK-NOT: {{vdiv|vmul}}
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define void @t5() nounwind {
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entry:
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%tmp = load i32, i32* @iin, align 4
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%vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
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%vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
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%vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
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%div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
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tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
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ret void
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}
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; Test quadword.
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; CHECK: t6
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; CHECK-NOT: {{vdiv|vmul}}
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define void @t6() nounwind {
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entry:
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%tmp = load i32, i32* @iin, align 4
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%vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
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%vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
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%vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
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%vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %tmp, i32 3
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%vcvt.i = sitofp <4 x i32> %vecinit6.i to <4 x float>
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%div.i = fdiv <4 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
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tail call void @foo_float32x4_t(<4 x float> %div.i) nounwind
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ret void
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}
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declare void @foo_float32x4_t(<4 x float>)
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define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
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; CHECK-LABEL: fix_unsigned_i16_to_float:
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; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}}
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; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1
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%conv = uitofp <4 x i16> %in to <4 x float>
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%shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
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ret <4 x float> %shift
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}
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define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
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; CHECK-LABEL: fix_signed_i16_to_float:
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; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}}
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; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1
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%conv = sitofp <4 x i16> %in to <4 x float>
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%shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
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ret <4 x float> %shift
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}
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define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
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; CHECK-LABEL: fix_i64_to_float:
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; CHECK: bl
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; CHECK: bl
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%conv = uitofp <2 x i64> %in to <2 x float>
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%shift = fdiv <2 x float> %conv, <float 2.0, float 2.0>
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ret <2 x float> %shift
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}
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define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
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; CHECK-LABEL: fix_i64_to_double:
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; CHECK: bl
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; CHECK: bl
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%conv = uitofp <2 x i64> %in to <2 x double>
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%shift = fdiv <2 x double> %conv, <double 2.0, double 2.0>
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ret <2 x double> %shift
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}
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; Don't combine with 8 lanes. Just make sure things don't crash.
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; CHECK-LABEL: test7
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define <8 x float> @test7(<8 x i32> %in) nounwind {
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entry:
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%vcvt.i = sitofp <8 x i32> %in to <8 x float>
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%div.i = fdiv <8 x float> %vcvt.i, <float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0, float 8.0>
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ret <8 x float> %div.i
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}
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; Can combine splat with an undef.
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; CHECK-LABEL: test8
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; CHECK: vcvt.f32.s32 q{{[0-9]+}}, q{{[0-9]+}}, #1
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define <4 x float> @test8(<4 x i32> %in) {
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%vcvt.i = sitofp <4 x i32> %in to <4 x float>
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%div.i = fdiv <4 x float> %vcvt.i, <float 2.0, float 2.0, float 2.0, float undef>
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ret <4 x float> %div.i
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}
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; CHECK-LABEL: test_illegal_int_to_fp:
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; CHECK: vcvt.f32.s32
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define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) {
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%conv = sitofp <3 x i32> %in to <3 x float>
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%res = fdiv <3 x float> %conv, <float 4.0, float 4.0, float 4.0>
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ret <3 x float> %res
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}
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