53 lines
1.7 KiB
LLVM
53 lines
1.7 KiB
LLVM
; RUN: llc -march=hexagon < %s 2>&1 | FileCheck %s
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; Generating a compound instruction with a constant is not profitable.
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; The constant needs to be kept in a register before it is fed to compound
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; instruction.
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; Before, we are generating
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; ra = #65820;
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; rb = lsr(rb, #8);
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; rc ^= and (rb, ra)
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; Now, we are generating
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; ra = and (#65820, lsr(ra, #8));
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; rb = xor(rb, ra)
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; CHECK: and(##65280,lsr(r
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; CHECK-NOT : ^= and
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define dso_local zeroext i16 @test_compound(i16 zeroext %varA, i16 zeroext %varB) local_unnamed_addr #0 {
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entry:
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%tmp = zext i16 %varB to i32
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%tmp1 = and i16 %varA, 255
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%tmp2 = zext i16 %tmp1 to i32
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%.masked.i = and i32 %tmp, 255
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%tmp3 = xor i32 %.masked.i, %tmp2
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%tmp4 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp3, i32 255) #2
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%tmp5 = trunc i64 %tmp4 to i32
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%tmp6 = and i32 %tmp5, 255
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%tmp7 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp6, i32 81922) #2
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%tmp8 = trunc i64 %tmp7 to i32
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%tmp9 = xor i32 %tmp8, %tmp
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%tmp10 = lshr i32 %tmp9, 8
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%tmp11 = lshr i16 %varA, 8
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%conv2 = zext i16 %tmp11 to i32
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%tmp12 = and i32 %tmp10, 65280
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%.masked.i7 = and i32 %tmp10, 255
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%tmp13 = xor i32 %.masked.i7, %conv2
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%tmp14 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp13, i32 255) #2
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%tmp15 = trunc i64 %tmp14 to i32
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%tmp16 = and i32 %tmp15, 255
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%tmp17 = tail call i64 @llvm.hexagon.M4.pmpyw(i32 %tmp16, i32 81922) #2
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%tmp18 = trunc i64 %tmp17 to i32
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%tmp19 = xor i32 %tmp12, %tmp18
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%tmp20 = lshr i32 %tmp19, 8
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%tmp21 = trunc i32 %tmp20 to i16
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ret i16 %tmp21
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M4.pmpyw(i32, i32) #1
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv65" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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