67 lines
1.9 KiB
LLVM
67 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; Even though general vector types are not supported in PTX, we can still
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; optimize loads/stores with pseudo-vector instructions of the form:
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;
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; ld.v2.f32 {%f0, %f1}, [%r0]
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;
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; which will load two floats at once into scalar registers.
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define void @foo(<2 x float>* %a) {
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; CHECK: .func foo
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; CHECK: ld.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = load <2 x float>, <2 x float>* %a
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%t2 = fmul <2 x float> %t1, %t1
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store <2 x float> %t2, <2 x float>* %a
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ret void
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}
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define void @foo2(<4 x float>* %a) {
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; CHECK: .func foo2
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; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = load <4 x float>, <4 x float>* %a
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%t2 = fmul <4 x float> %t1, %t1
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store <4 x float> %t2, <4 x float>* %a
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ret void
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}
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define void @foo3(<8 x float>* %a) {
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; CHECK: .func foo3
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; CHECK: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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; CHECK-NEXT: ld.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
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%t1 = load <8 x float>, <8 x float>* %a
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%t2 = fmul <8 x float> %t1, %t1
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store <8 x float> %t2, <8 x float>* %a
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ret void
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}
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define void @foo4(<2 x i32>* %a) {
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; CHECK: .func foo4
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; CHECK: ld.v2.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}}
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%t1 = load <2 x i32>, <2 x i32>* %a
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%t2 = mul <2 x i32> %t1, %t1
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store <2 x i32> %t2, <2 x i32>* %a
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ret void
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}
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define void @foo5(<4 x i32>* %a) {
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; CHECK: .func foo5
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; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
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%t1 = load <4 x i32>, <4 x i32>* %a
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%t2 = mul <4 x i32> %t1, %t1
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store <4 x i32> %t2, <4 x i32>* %a
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ret void
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}
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define void @foo6(<8 x i32>* %a) {
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; CHECK: .func foo6
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; CHECK: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
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; CHECK-NEXT: ld.v4.u32 {%r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}}
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%t1 = load <8 x i32>, <8 x i32>* %a
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%t2 = mul <8 x i32> %t1, %t1
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store <8 x i32> %t2, <8 x i32>* %a
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ret void
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}
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