126 lines
3.0 KiB
LLVM
126 lines
3.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define zeroext i32 @test1() {
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entry:
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%0 = tail call i32 @llvm.ppc.tbegin(i32 0)
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ret i32 %0
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; CHECK-LABEL: @test1
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; CHECK: tbegin. 0
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; CHECK: mfocrf [[REGISTER1:[0-9]+]], 128
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; CHECK: rlwinm [[REGISTER2:[0-9]+]], [[REGISTER1]], 3, 31, 31
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; CHECK: xori {{[0-9]+}}, [[REGISTER2]], 1
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}
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declare i32 @llvm.ppc.tbegin(i32) #1
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define zeroext i32 @test2() {
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entry:
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%0 = tail call i32 @llvm.ppc.tend(i32 0)
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ret i32 %0
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; CHECK-LABEL: @test2
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; CHECK: tend. 0
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; CHECK: mfocrf {{[0-9]+}}, 128
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}
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declare i32 @llvm.ppc.tend(i32)
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define void @test3() {
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entry:
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%0 = tail call i32 @llvm.ppc.tabort(i32 0)
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%1 = tail call i32 @llvm.ppc.tabortdc(i32 0, i32 1, i32 2)
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%2 = tail call i32 @llvm.ppc.tabortdci(i32 0, i32 1, i32 2)
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%3 = tail call i32 @llvm.ppc.tabortwc(i32 0, i32 1, i32 2)
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%4 = tail call i32 @llvm.ppc.tabortwci(i32 0, i32 1, i32 2)
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ret void
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; CHECK-LABEL: @test3
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; CHECK: tabort. {{[0-9]+}}
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; CHECK: tabortdc. 0, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: tabortdci. 0, {{[0-9]+}}, 2
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; CHECK: tabortwc. 0, {{[0-9]+}}, {{[0-9]+}}
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; CHECK: tabortwci. 0, {{[0-9]+}}, 2
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}
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declare i32 @llvm.ppc.tabort(i32)
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declare i32 @llvm.ppc.tabortdc(i32, i32, i32)
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declare i32 @llvm.ppc.tabortdci(i32, i32, i32)
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declare i32 @llvm.ppc.tabortwc(i32, i32, i32)
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declare i32 @llvm.ppc.tabortwci(i32, i32, i32)
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define void @test4() {
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entry:
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%0 = tail call i32 @llvm.ppc.tendall()
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%1 = tail call i32 @llvm.ppc.tresume()
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%2 = tail call i32 @llvm.ppc.tsuspend()
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ret void
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; CHECK-LABEL: @test4
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; CHECK: tend. 1
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; CHECK: tsr. 1
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; CHECK: tsr. 0
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}
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declare i32 @llvm.ppc.tendall()
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declare i32 @llvm.ppc.tresume()
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declare i32 @llvm.ppc.tsuspend()
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define void @test5(i64 %v) {
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entry:
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tail call void @llvm.ppc.set.texasr(i64 %v)
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tail call void @llvm.ppc.set.texasru(i64 %v)
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tail call void @llvm.ppc.set.tfhar(i64 %v)
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tail call void @llvm.ppc.set.tfiar(i64 %v)
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ret void
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; CHECK-LABEL: @test5
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; CHECK: mtspr 130, [[REG1:[0-9]+]]
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; CHECK: mtspr 131, [[REG2:[0-9]+]]
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; CHECK: mtspr 128, [[REG3:[0-9]+]]
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; CHECK: mtspr 129, [[REG4:[0-9]+]]
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}
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define i64 @test6() {
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entry:
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%0 = tail call i64 @llvm.ppc.get.texasr()
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ret i64 %0
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; CHECK-LABEL: @test6
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; CHECK: mfspr [[REG1:[0-9]+]], 130
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}
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define i64 @test7() {
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entry:
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%0 = tail call i64 @llvm.ppc.get.texasru()
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ret i64 %0
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; CHECK-LABEL: @test7
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; CHECK: mfspr [[REG1:[0-9]+]], 131
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}
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define i64 @test8() {
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entry:
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%0 = tail call i64 @llvm.ppc.get.tfhar()
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ret i64 %0
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; CHECK-LABEL: @test8
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; CHECK: mfspr [[REG1:[0-9]+]], 128
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}
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define i64 @test9() {
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entry:
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%0 = tail call i64 @llvm.ppc.get.tfiar()
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ret i64 %0
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; CHECK-LABEL: @test9
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; CHECK: mfspr [[REG1:[0-9]+]], 129
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}
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declare void @llvm.ppc.set.texasr(i64)
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declare void @llvm.ppc.set.texasru(i64)
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declare void @llvm.ppc.set.tfhar(i64)
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declare void @llvm.ppc.set.tfiar(i64)
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declare i64 @llvm.ppc.get.texasr()
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declare i64 @llvm.ppc.get.texasru()
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declare i64 @llvm.ppc.get.tfhar()
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declare i64 @llvm.ppc.get.tfiar()
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