189 lines
6.2 KiB
LLVM
189 lines
6.2 KiB
LLVM
; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr7 -enable-unsafe-fp-math < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK -check-prefix=CHECK-PWR
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; RUN: llc -verify-machineinstrs -O3 -mcpu=a2q -enable-unsafe-fp-math < %s | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=CHECK -check-prefix=CHECK-QPX
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Verify that the first two adds are independent regardless of how the inputs are
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; commuted. The destination registers are used as source registers for the third add.
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define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds1:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %t0, %x2
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%t2 = fadd float %t1, %x3
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ret float %t2
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}
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define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds2:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %x2, %t0
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%t2 = fadd float %t1, %x3
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ret float %t2
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}
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define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds3:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %t0, %x2
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%t2 = fadd float %x3, %t1
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ret float %t2
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}
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define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
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; CHECK-LABEL: reassociate_adds4:
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; CHECK: # %bb.0:
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; CHECK: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK: fadds [[REG1:[0-9]+]], 3, 4
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; CHECK: fadds 1, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %x2, %t0
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%t2 = fadd float %x3, %t1
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ret float %t2
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}
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; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not
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; produced because that would cost more compile time.
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define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {
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; CHECK-LABEL: reassociate_adds5:
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; CHECK: # %bb.0:
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; CHECK-DAG: fadds [[REG12:[0-9]+]], 5, 6
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; CHECK-DAG: fadds [[REG0:[0-9]+]], 1, 2
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; CHECK-DAG: fadds [[REG11:[0-9]+]], 3, 4
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; CHECK: fadds [[REG13:[0-9]+]], [[REG12]], 7
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; CHECK-DAG: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]
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; CHECK-DAG: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]
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; CHECK: fadds 1, [[REG2]], 8
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; CHECK-NEXT: blr
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%t0 = fadd float %x0, %x1
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%t1 = fadd float %t0, %x2
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%t2 = fadd float %t1, %x3
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%t3 = fadd float %t2, %x4
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%t4 = fadd float %t3, %x5
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%t5 = fadd float %t4, %x6
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%t6 = fadd float %t5, %x7
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ret float %t6
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}
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; Verify that we reassociate vector instructions too.
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define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds1:
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; CHECK: # %bb.0:
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; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
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; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
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; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd <4 x float> %x0, %x1
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%t1 = fadd <4 x float> %t0, %x2
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%t2 = fadd <4 x float> %t1, %x3
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ret <4 x float> %t2
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}
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define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds2:
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; CHECK: # %bb.0:
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; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
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; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
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; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd <4 x float> %x0, %x1
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%t1 = fadd <4 x float> %x2, %t0
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%t2 = fadd <4 x float> %t1, %x3
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ret <4 x float> %t2
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}
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define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds3:
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; CHECK: # %bb.0:
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; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
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; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
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; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd <4 x float> %x0, %x1
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%t1 = fadd <4 x float> %t0, %x2
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%t2 = fadd <4 x float> %x3, %t1
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ret <4 x float> %t2
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}
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define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; CHECK-LABEL: vector_reassociate_adds4:
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; CHECK: # %bb.0:
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; CHECK-QPX: qvfadds [[REG0:[0-9]+]], 1, 2
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; CHECK-QPX: qvfadds [[REG1:[0-9]+]], 3, 4
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; CHECK-QPX: qvfadds 1, [[REG0]], [[REG1]]
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; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35
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; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37
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; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]
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; CHECK-NEXT: blr
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%t0 = fadd <4 x float> %x0, %x1
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%t1 = fadd <4 x float> %x2, %t0
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%t2 = fadd <4 x float> %x3, %t1
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ret <4 x float> %t2
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}
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define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) {
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%t0 = fdiv float %x0, %x1
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%t1 = fadd float %x2, %t0
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%t2 = fadd float %x3, %t1
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ret float %t2
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}
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define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
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%t0 = fdiv float %x0, %x1
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%t1 = fmul float %x2, %t0
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%t2 = fmul float %x3, %t1
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ret float %t2
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}
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define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {
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%t0 = fdiv double %x0, %x1
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%t1 = fadd double %x2, %t0
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%t2 = fadd double %x3, %t1
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ret double %t2
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}
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define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
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%t0 = fdiv double %x0, %x1
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%t1 = fmul double %x2, %t0
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%t2 = fmul double %x3, %t1
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ret double %t2
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}
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