llvm-project/llvm/test/MC/Disassembler
Ana Pazos 0a5fcefa31 [RISCV] Fix disassembling of fence instruction with invalid field
Summary:
Instruction with 0 in fence field being disassembled as fence , iorw.
Printing "unknown" to match GAS behavior.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.

Reviewers: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51828

llvm-svn: 344309
2018-10-11 22:49:13 +00:00
..
AArch64 [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
AMDGPU AMDGPU: Fix v_dot{4, 8}* instruction encoding 2018-05-15 19:32:47 +00:00
ARC [ARC] Prevent InstPrinter from crashing on unknown condition codes. 2018-09-06 19:58:26 +00:00
ARM [ARM][v8.5A] Add speculation barriers SSBB and PSSBB 2018-09-28 08:27:56 +00:00
Hexagon NFC - Various typo fixes in tests 2018-07-04 13:28:39 +00:00
Lanai
Mips [mips] Add missing instructions 2018-08-29 11:35:03 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
RISCV [RISCV] Fix disassembling of fence instruction with invalid field 2018-10-11 22:49:13 +00:00
Sparc
SystemZ [SystemZ] Add support for IBM z14 processor (3/3) 2017-07-17 17:44:20 +00:00
WebAssembly [WebAssembly] v8x16.shuffle 2018-09-07 21:54:46 +00:00
X86 [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16. 2018-10-02 18:16:19 +00:00
XCore