140 lines
4.6 KiB
ArmAsm
140 lines
4.6 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -riscv-no-aliases \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+f \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -riscv-no-aliases \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+f \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
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# RUN: | llvm-objdump -d -mattr=+f -riscv-no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
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# RUN: | llvm-objdump -d -mattr=+f - \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
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# RUN: | llvm-objdump -d -mattr=+f -riscv-no-aliases - \
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# RUN: | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
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# RUN: | llvm-objdump -d -mattr=+f - \
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# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
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##===----------------------------------------------------------------------===##
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## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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##===----------------------------------------------------------------------===##
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# TODO flw
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# TODO fsw
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# CHECK-INST: fsgnj.s ft0, ft1, ft1
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# CHECK-ALIAS: fmv.s ft0, ft1
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fmv.s f0, f1
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# CHECK-INST: fsgnjx.s ft1, ft2, ft2
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# CHECK-ALIAS: fabs.s ft1, ft2
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fabs.s f1, f2
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# CHECK-INST: fsgnjn.s ft2, ft3, ft3
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# CHECK-ALIAS: fneg.s ft2, ft3
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fneg.s f2, f3
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# CHECK-INST: flt.s tp, ft6, ft5
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# CHECK-ALIAS: flt.s tp, ft6, ft5
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fgt.s x4, f5, f6
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# CHECK-INST: fle.s t2, fs1, fs0
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# CHECK-ALIAS: fle.s t2, fs1, fs0
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fge.s x7, f8, f9
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# The following instructions actually alias instructions from the base ISA.
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# However, it only makes sense to support them when the F extension is enabled.
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# CHECK-INST: csrrs t0, fcsr, zero
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# CHECK-ALIAS: frcsr t0
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frcsr x5
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# CHECK-INST: csrrw t1, fcsr, t2
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# CHECK-ALIAS: fscsr t1, t2
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fscsr x6, x7
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# CHECK-INST: csrrw zero, fcsr, t3
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# CHECK-ALIAS: fscsr t3
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fscsr x28
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# CHECK-INST: csrrs t4, frm, zero
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# CHECK-ALIAS: frrm t4
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frrm x29
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# CHECK-INST: csrrw t5, frm, t4
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# CHECK-ALIAS: fsrm t5, t4
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fsrm x30, x29
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# CHECK-INST: csrrw zero, frm, t6
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# CHECK-ALIAS: fsrm t6
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fsrm x31
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# CHECK-INST: csrrwi a0, frm, 31
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# CHECK-ALIAS: fsrmi a0, 31
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fsrmi x10, 0x1f
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# CHECK-INST: csrrwi zero, frm, 30
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# CHECK-ALIAS: fsrmi 30
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fsrmi 0x1e
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# CHECK-INST: csrrs a1, fflags, zero
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# CHECK-ALIAS: frflags a1
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frflags x11
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# CHECK-INST: csrrw a2, fflags, a1
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# CHECK-ALIAS: fsflags a2, a1
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fsflags x12, x11
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# CHECK-INST: csrrw zero, fflags, a3
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# CHECK-ALIAS: fsflags a3
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fsflags x13
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# CHECK-INST: csrrwi a4, fflags, 29
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# CHECK-ALIAS: fsflagsi a4, 29
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fsflagsi x14, 0x1d
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# CHECK-INST: csrrwi zero, fflags, 28
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# CHECK-ALIAS: fsflagsi 28
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fsflagsi 0x1c
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# CHECK-INST: fmv.x.w a2, fs7
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# CHECK-ALIAS: fmv.x.w a2, fs7
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fmv.x.s a2, fs7
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# CHECK-INST: fmv.w.x ft1, a6
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# CHECK-ALIAS: fmv.w.x ft1, a6
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fmv.s.x ft1, a6
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##===----------------------------------------------------------------------===##
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## Aliases which omit the rounding mode.
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##===----------------------------------------------------------------------===##
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# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
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# CHECK-ALIAS: fmadd.s fa0, fa1, fa2, fa3{{[[:space:]]}}
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fmadd.s f10, f11, f12, f13
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# CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, dyn
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# CHECK-ALIAS: fmsub.s fa4, fa5, fa6, fa7{{[[:space:]]}}
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fmsub.s f14, f15, f16, f17
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# CHECK-INST: fnmsub.s fs2, fs3, fs4, fs5, dyn
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# CHECK-ALIAS: fnmsub.s fs2, fs3, fs4, fs5{{[[:space:]]}}
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fnmsub.s f18, f19, f20, f21
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# CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, dyn
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# CHECK-ALIAS: fnmadd.s fs6, fs7, fs8, fs9{{[[:space:]]}}
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fnmadd.s f22, f23, f24, f25
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# CHECK-INST: fadd.s fs10, fs11, ft8, dyn
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# CHECK-ALIAS: fadd.s fs10, fs11, ft8{{[[:space:]]}}
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fadd.s f26, f27, f28
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# CHECK-INST: fsub.s ft9, ft10, ft11, dyn
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# CHECK-ALIAS: fsub.s ft9, ft10, ft11{{[[:space:]]}}
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fsub.s f29, f30, f31
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# CHECK-INST: fmul.s ft0, ft1, ft2, dyn
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# CHECK-ALIAS: fmul.s ft0, ft1, ft2{{[[:space:]]}}
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fmul.s ft0, ft1, ft2
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# CHECK-INST: fdiv.s ft3, ft4, ft5, dyn
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# CHECK-ALIAS: fdiv.s ft3, ft4, ft5{{[[:space:]]}}
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fdiv.s ft3, ft4, ft5
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# CHECK-INST: fsqrt.s ft6, ft7, dyn
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# CHECK-ALIAS: fsqrt.s ft6, ft7{{[[:space:]]}}
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fsqrt.s ft6, ft7
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# CHECK-INST: fcvt.w.s a0, fs5, dyn
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# CHECK-ALIAS: fcvt.w.s a0, fs5{{[[:space:]]}}
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fcvt.w.s a0, fs5
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# CHECK-INST: fcvt.wu.s a1, fs6, dyn
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# CHECK-ALIAS: fcvt.wu.s a1, fs6{{[[:space:]]}}
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fcvt.wu.s a1, fs6
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# CHECK-INST: fcvt.s.w ft11, a4, dyn
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# CHECK-ALIAS: fcvt.s.w ft11, a4{{[[:space:]]}}
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fcvt.s.w ft11, a4
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# CHECK-INST: fcvt.s.wu ft0, a5, dyn
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# CHECK-ALIAS: fcvt.s.wu ft0, a5{{[[:space:]]}}
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fcvt.s.wu ft0, a5
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