112 lines
3.9 KiB
LLVM
112 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -instcombine < %s | FileCheck %s
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define i64 @sel_false_val_is_a_masked_shl_of_true_val1(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val1(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw nsw i32 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
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; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
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; CHECK-NEXT: ret i64 [[TMP5]]
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;
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%1 = and i32 %x, 15
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%2 = shl nuw nsw i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %1, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_shl_of_true_val2(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_shl_of_true_val2(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, 15
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%2 = shl nuw nsw i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %2, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_lshr_of_true_val1(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val1(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 60
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; CHECK-NEXT: [[TMP2:%.*]] = lshr exact i32 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
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; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
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; CHECK-NEXT: ret i64 [[TMP5]]
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;
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%1 = and i32 %x, 60
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%2 = lshr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %1, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_lshr_of_true_val2(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_lshr_of_true_val2(
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; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, 60
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%2 = lshr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %2, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_ashr_of_true_val1(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val1(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], -2147483588
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; CHECK-NEXT: [[TMP2:%.*]] = ashr exact i32 [[TMP1]], 2
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[NARROW]] to i64
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; CHECK-NEXT: [[TMP5:%.*]] = ashr i64 [[Y:%.*]], [[TMP4]]
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; CHECK-NEXT: ret i64 [[TMP5]]
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;
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%1 = and i32 %x, -2147483588
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%2 = ashr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %1, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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define i64 @sel_false_val_is_a_masked_ashr_of_true_val2(i32 %x, i64 %y) {
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; CHECK-LABEL: @sel_false_val_is_a_masked_ashr_of_true_val2(
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; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]]
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; CHECK-NEXT: ret i64 [[TMP4]]
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;
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%1 = and i32 %x, -2147483588
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%2 = ashr i32 %1, 2
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%3 = zext i32 %2 to i64
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%4 = icmp eq i32 %2, 0
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%5 = ashr i64 %y, %3
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%6 = select i1 %4, i64 %y, i64 %5
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ret i64 %6
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}
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