539 lines
13 KiB
LLVM
539 lines
13 KiB
LLVM
; RUN: opt < %s -jump-threading -S | FileCheck %s
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; RUN: opt < %s -aa-pipeline=basic-aa -passes=jump-threading -S | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin7"
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; Test that we can thread through the block with the partially redundant load (%2).
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; rdar://6402033
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define i32 @test1(i32* %P) nounwind {
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; CHECK-LABEL: @test1(
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entry:
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%0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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br i1 %1, label %bb1, label %bb
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bb: ; preds = %entry
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; CHECK: bb1.thread:
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; CHECK: store
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; CHECK: br label %bb3
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store i32 42, i32* %P, align 4
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br label %bb1
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bb1: ; preds = %entry, %bb
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ] ; <i32> [#uses=2]
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%2 = load i32, i32* %P, align 4 ; <i32> [#uses=1]
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%3 = icmp sgt i32 %2, 36 ; <i1> [#uses=1]
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br i1 %3, label %bb3, label %bb2
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bb2: ; preds = %bb1
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%4 = tail call i32 (...) @f2() nounwind ; <i32> [#uses=0]
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ret i32 %res.0
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bb3: ; preds = %bb1
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; CHECK: bb3:
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; CHECK: %res.01 = phi i32 [ 1, %bb1.thread ], [ 0, %bb1 ]
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; CHECK: ret i32 %res.01
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ret i32 %res.0
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}
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declare i32 @f1(...)
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declare i32 @f2(...)
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;; Check that we preserve TBAA information.
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; rdar://11039258
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define i32 @test2(i32* %P) nounwind {
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; CHECK-LABEL: @test2(
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entry:
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%0 = tail call i32 (...) @f1() nounwind ; <i32> [#uses=1]
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%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
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br i1 %1, label %bb1, label %bb
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bb: ; preds = %entry
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; CHECK: bb1.thread:
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; CHECK: store{{.*}}, !tbaa !0
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; CHECK: br label %bb3
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store i32 42, i32* %P, align 4, !tbaa !0
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br label %bb1
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bb1: ; preds = %entry, %bb
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%2 = load i32, i32* %P, align 4, !tbaa !0
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%3 = icmp sgt i32 %2, 36
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br i1 %3, label %bb3, label %bb2
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bb2: ; preds = %bb1
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%4 = tail call i32 (...) @f2() nounwind
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ret i32 %res.0
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bb3: ; preds = %bb1
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; CHECK: bb3:
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; CHECK: %res.01 = phi i32 [ 1, %bb1.thread ], [ 0, %bb1 ]
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; CHECK: ret i32 %res.01
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ret i32 %res.0
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}
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define i32 @test3(i8** %x, i1 %f) {
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; Correctly thread loads of different (but compatible) types, placing bitcasts
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; as necessary in the predecessors. This is especially tricky because the same
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; predecessor ends up with two entries in the PHI node and they must share
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; a single cast.
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; CHECK-LABEL: @test3(
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entry:
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%0 = bitcast i8** %x to i32**
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%1 = load i32*, i32** %0, align 8
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br i1 %f, label %if.end57, label %if.then56
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; CHECK: %[[LOAD:.*]] = load i32*, i32**
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; CHECK: %[[CAST:.*]] = bitcast i32* %[[LOAD]] to i8*
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if.then56:
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br label %if.end57
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if.end57:
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%2 = load i8*, i8** %x, align 8
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%tobool59 = icmp eq i8* %2, null
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br i1 %tobool59, label %return, label %if.then60
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; CHECK: %[[PHI:.*]] = phi i8* [ %[[CAST]], %[[PRED:[^ ]+]] ], [ %[[CAST]], %[[PRED]] ]
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; CHECK-NEXT: %[[CMP:.*]] = icmp eq i8* %[[PHI]], null
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; CHECK-NEXT: br i1 %[[CMP]]
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if.then60:
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ret i32 42
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return:
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ret i32 13
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}
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define i32 @test4(i32* %P) {
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; CHECK-LABEL: @test4(
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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; CHECK: bb1.thread:
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; CHECK: store atomic
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; CHECK: br label %bb3
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store atomic i32 42, i32* %P unordered, align 4
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br label %bb1
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bb1:
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; CHECK: bb1:
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; CHECK-NOT: phi
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; CHECK: load atomic
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P unordered, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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define i32 @test5(i32* %P) {
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; Negative test
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; CHECK-LABEL: @test5(
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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; CHECK: bb:
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; CHECK-NEXT: store atomic i32 42, i32* %P release, align 4
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; CHECK-NEXT: br label %bb1
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store atomic i32 42, i32* %P release, align 4
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br label %bb1
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bb1:
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; CHECK: bb1:
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; CHECK-NEXT: %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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; CHECK-NEXT: %v2 = load atomic i32, i32* %P acquire, align 4
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; CHECK-NEXT: %v3 = icmp sgt i32 %v2, 36
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; CHECK-NEXT: br i1 %v3, label %bb3, label %bb2
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P acquire, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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define i32 @test6(i32* %P) {
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; Negative test
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; CHECK-LABEL: @test6(
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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; CHECK: bb:
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; CHECK-NEXT: store i32 42, i32* %P
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; CHECK-NEXT: br label %bb1
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store i32 42, i32* %P
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br label %bb1
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bb1:
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; CHECK: bb1:
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; CHECK-NEXT: %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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; CHECK-NEXT: %v2 = load atomic i32, i32* %P acquire, align 4
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; CHECK-NEXT: %v3 = icmp sgt i32 %v2, 36
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; CHECK-NEXT: br i1 %v3, label %bb3, label %bb2
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P acquire, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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define i32 @test7(i32* %P) {
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; Negative test
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; CHECK-LABEL: @test7(
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entry:
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%v0 = tail call i32 (...) @f1()
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%v1 = icmp eq i32 %v0, 0
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br i1 %v1, label %bb1, label %bb
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bb:
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; CHECK: bb:
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; CHECK-NEXT: %val = load i32, i32* %P
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; CHECK-NEXT: br label %bb1
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%val = load i32, i32* %P
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br label %bb1
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bb1:
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; CHECK: bb1:
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; CHECK-NEXT: %res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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; CHECK-NEXT: %v2 = load atomic i32, i32* %P acquire, align 4
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; CHECK-NEXT: %v3 = icmp sgt i32 %v2, 36
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; CHECK-NEXT: br i1 %v3, label %bb3, label %bb2
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%res.0 = phi i32 [ 1, %bb ], [ 0, %entry ]
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%v2 = load atomic i32, i32* %P acquire, align 4
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%v3 = icmp sgt i32 %v2, 36
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br i1 %v3, label %bb3, label %bb2
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bb2:
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%v4 = tail call i32 (...) @f2()
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ret i32 %res.0
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bb3:
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ret i32 %res.0
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}
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; Make sure we merge the aliasing metadata. (If we don't, we have a load
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; with the wrong metadata, so the branch gets incorrectly eliminated.)
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define void @test8(i32*, i32*, i32*) {
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; CHECK-LABEL: @test8(
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; CHECK: %a = load i32, i32* %0, !range !4
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; CHECK-NEXT: store i32 %a
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; CHECK: br i1 %c
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%a = load i32, i32* %0, !tbaa !0, !range !4, !alias.scope !9, !noalias !10
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%b = load i32, i32* %0, !range !5
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store i32 %a, i32* %1
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%c = icmp eq i32 %b, 8
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br i1 %c, label %ret1, label %ret2
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ret1:
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ret void
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ret2:
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%xxx = tail call i32 (...) @f1() nounwind
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ret void
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}
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; Make sure we merge/PRE aliasing metadata correctly. That means that
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; we need to remove metadata from the existing load, and add appropriate
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; metadata to the newly inserted load.
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define void @test9(i32*, i32*, i32*, i1 %c) {
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; CHECK-LABEL: @test9(
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br i1 %c, label %d1, label %d2
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; CHECK: d1:
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; CHECK-NEXT: %a = load i32, i32* %0{{$}}
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d1:
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%a = load i32, i32* %0, !range !4, !alias.scope !9, !noalias !10
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br label %d3
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; CHECK: d2:
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; CHECK-NEXT: %xxxx = tail call i32 (...) @f1()
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; CHECK-NEXT: %b.pr = load i32, i32* %0, !tbaa !0{{$}}
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d2:
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%xxxx = tail call i32 (...) @f1() nounwind
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br label %d3
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d3:
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%p = phi i32 [ 1, %d2 ], [ %a, %d1 ]
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%b = load i32, i32* %0, !tbaa !0
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store i32 %p, i32* %1
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%c2 = icmp eq i32 %b, 8
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br i1 %c2, label %ret1, label %ret2
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ret1:
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ret void
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ret2:
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%xxx = tail call i32 (...) @f1() nounwind
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ret void
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}
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define i32 @fn_noalias(i1 %c2,i64* noalias %P, i64* noalias %P2) {
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; CHECK-LABEL: @fn_noalias
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; CHECK-LABEL: cond1:
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; CHECK: %[[LD1:.*]] = load i64, i64* %P
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; CHECK: br i1 %c, label %[[THREAD:.*]], label %end
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; CHECK-LABEL: cond2:
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; CHECK: %[[LD2:.*]] = load i64, i64* %P
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; CHECK-LABEL: cond3:
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; CHECK: %[[PHI:.*]] = phi i64 [ %[[LD1]], %[[THREAD]] ], [ %[[LD2]], %cond2 ]
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; CHECK: call void @fn3(i64 %[[PHI]])
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entry:
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br i1 %c2, label %cond2, label %cond1
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cond1:
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%l1 = load i64, i64* %P
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store i64 42, i64* %P2
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%c = icmp eq i64 %l1, 0
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br i1 %c, label %cond2, label %end
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cond2:
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%l2 = load i64, i64* %P
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call void @fn2(i64 %l2)
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%c3 = icmp eq i64 %l2, 0
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br i1 %c3, label %cond3, label %end
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cond3:
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call void @fn3(i64 %l2)
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br label %end
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end:
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ret i32 0
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}
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; This tests if we can thread from %sw.bb.i to %do.body.preheader.i67 through
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; %sw.bb21.i. To make this happen, %l2 should be detected as a partically
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; redundant load with %l3 across the store to %phase in %sw.bb21.i.
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%struct.NEXT_MOVE = type { i32, i32, i32* }
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@hash_move = unnamed_addr global [65 x i32] zeroinitializer, align 4
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@current_move = internal global [65 x i32] zeroinitializer, align 4
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@last = internal unnamed_addr global [65 x i32*] zeroinitializer, align 8
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@next_status = internal unnamed_addr global [65 x %struct.NEXT_MOVE] zeroinitializer, align 8
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define fastcc i32 @Search(i64 %idxprom.i, i64 %idxprom.i89, i32 %c) {
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; CHECK-LABEL: @Search
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; CHECK-LABEL: sw.bb.i:
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; CHECK: %[[LD1:.*]] = load i32, i32* %arrayidx185, align 4
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; CHECK: %[[C1:.*]] = icmp eq i32 %[[LD1]], 0
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; CHECK: br i1 %[[C1]], label %sw.bb21.i.thread, label %if.then.i64
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; CHECK-LABEL: sw.bb21.i.thread:
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; CHECK: br label %[[THREAD_TO:.*]]
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; CHECK-LABEL: sw.bb21.i:
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; CHECK: %[[LD2:.*]] = load i32, i32* %arrayidx185, align 4
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; CHECK: %[[C2:.*]] = icmp eq i32 %[[LD2]], 0
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; CHECK:br i1 %[[C2]], label %[[THREAD_TO]], label %cleanup
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entry:
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%arrayidx185 = getelementptr inbounds [65 x i32], [65 x i32]* @hash_move, i64 0, i64 %idxprom.i
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%arrayidx307 = getelementptr inbounds [65 x i32], [65 x i32]* @current_move, i64 0, i64 %idxprom.i
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%arrayidx89 = getelementptr inbounds [65 x i32*], [65 x i32*]* @last, i64 0, i64 %idxprom.i
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%phase = getelementptr inbounds [65 x %struct.NEXT_MOVE], [65 x %struct.NEXT_MOVE]* @next_status, i64 0, i64 %idxprom.i, i32 0
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br label %cond.true282
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cond.true282:
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switch i32 %c, label %sw.default.i [
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i32 1, label %sw.bb.i
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i32 0, label %sw.bb21.i
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]
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sw.default.i:
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br label %cleanup
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sw.bb.i:
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%call.i62 = call fastcc i32* @GenerateCheckEvasions()
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store i32* %call.i62, i32** %arrayidx89, align 8
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%l2 = load i32, i32* %arrayidx185, align 4
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%tobool.i63 = icmp eq i32 %l2, 0
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br i1 %tobool.i63, label %sw.bb21.i, label %if.then.i64
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if.then.i64: ; preds = %sw.bb.i
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store i32 7, i32* %phase, align 8
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store i32 %l2, i32* %arrayidx307, align 4
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%call16.i = call fastcc i32 @ValidMove(i32 %l2)
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%tobool17.i = icmp eq i32 %call16.i, 0
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br i1 %tobool17.i, label %if.else.i65, label %cleanup
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if.else.i65:
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call void @f65()
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br label %sw.bb21.i
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sw.bb21.i:
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store i32 10, i32* %phase, align 8
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%l3= load i32, i32* %arrayidx185, align 4
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%tobool27.i = icmp eq i32 %l3, 0
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br i1 %tobool27.i, label %do.body.preheader.i67, label %cleanup
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do.body.preheader.i67:
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call void @f67()
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ret i32 67
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cleanup:
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call void @Cleanup()
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ret i32 0
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}
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declare fastcc i32* @GenerateCheckEvasions()
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declare fastcc i32 @ValidMove(i32 %move)
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declare void @f67()
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declare void @Cleanup()
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declare void @f65()
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define i32 @fn_SinglePred(i1 %c2,i64* %P) {
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; CHECK-LABEL: @fn_SinglePred
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; CHECK-LABEL: entry:
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; CHECK: %[[L1:.*]] = load i64, i64* %P
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; CHECK: br i1 %c, label %cond3, label %cond1
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; CHECK-LABEL: cond2:
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; CHECK-NOT: load
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; CHECK: %[[PHI:.*]] = phi i64 [ %[[L1]], %cond1 ]
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; CHECK: call void @fn2(i64 %[[PHI]])
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; CHECK: br label %end
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; CHECK-LABEL: cond3:
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; CHECK: call void @fn2(i64 %l1)
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; CHECK: call void @fn3(i64 %l1)
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entry:
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%l1 = load i64, i64* %P
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%c = icmp eq i64 %l1, 0
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br i1 %c, label %cond2, label %cond1
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cond1:
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br i1 %c2, label %cond2, label %end
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cond2:
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%l2 = load i64, i64* %P
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call void @fn2(i64 %l2)
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%c3 = icmp eq i64 %l2, 0
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br i1 %c3, label %cond3, label %end
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cond3:
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call void @fn3(i64 %l2)
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br label %end
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end:
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ret i32 0
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}
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define i32 @fn_SinglePredMultihop(i1 %c1, i1 %c2,i64* %P) {
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; CHECK-LABEL: @fn_SinglePredMultihop
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; CHECK-LABEL: entry:
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; CHECK: %[[L1:.*]] = load i64, i64* %P
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; CHECK: br i1 %c0, label %cond3, label %cond0
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; CHECK-LABEL: cond2:
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; CHECK-NOT: load
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; CHECK: %[[PHI:.*]] = phi i64 [ %[[L1]], %cond1 ]
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; CHECK: call void @fn2(i64 %[[PHI]])
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; CHECK: br label %end
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; CHECK-LABEL: cond3:
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; CHECK: call void @fn2(i64 %l1)
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; CHECK: call void @fn3(i64 %l1)
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entry:
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%l1 = load i64, i64* %P
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%c0 = icmp eq i64 %l1, 0
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br i1 %c0, label %cond2, label %cond0
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cond0:
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br i1 %c1, label %cond1, label %end
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cond1:
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br i1 %c2, label %cond2, label %end
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cond2:
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%l2 = load i64, i64* %P
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call void @fn2(i64 %l2)
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%c3 = icmp eq i64 %l2, 0
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br i1 %c3, label %cond3, label %end
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cond3:
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call void @fn3(i64 %l2)
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br label %end
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end:
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ret i32 0
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}
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declare void @fn2(i64)
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declare void @fn3(i64)
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; Make sure we phi-translate and make the partially redundant load in
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; merge fully redudant and then we can jump-thread the block with the
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; store.
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;
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; CHECK-LABEL: define i32 @phi_translate_partial_redundant_loads(i32, i32*, i32*
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; CHECK: merge.thread:
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; CHECK: store
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; CHECK: br label %left_x
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;
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; CHECK: left_x:
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; CHECK-NEXT: ret i32 20
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define i32 @phi_translate_partial_redundant_loads(i32, i32*, i32*) {
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%cmp0 = icmp ne i32 %0, 0
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br i1 %cmp0, label %left, label %right
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left:
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store i32 1, i32* %1, align 4
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br label %merge
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right:
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br label %merge
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merge:
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%phiptr = phi i32* [ %1, %left ], [ %2, %right ]
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%newload = load i32, i32* %phiptr, align 4
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%cmp1 = icmp slt i32 %newload, 5
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br i1 %cmp1, label %left_x, label %right_x
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left_x:
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ret i32 20
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right_x:
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ret i32 10
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}
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!0 = !{!3, !3, i64 0}
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!1 = !{!"omnipotent char", !2}
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!2 = !{!"Simple C/C++ TBAA"}
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!3 = !{!"int", !1}
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!4 = !{ i32 0, i32 1 }
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!5 = !{ i32 8, i32 10 }
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!6 = !{!6}
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!7 = !{!7, !6}
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!8 = !{!8, !6}
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!9 = !{!7}
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!10 = !{!8}
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