Andrea Di Biagio b744abb4f6 [X86][BtVer2] Improved latency and throughput of float/vector loads and stores. ... This patch introduces the following changes to the btver2 scheduling model: - The number of micro opcodes for YMM loads and stores is now 2 (it was incorrectly set to 1 for both aligned and misaligned loads/stores). - Increased the number of AGU resource cycles for YMM loads and stores to 2cy (instead of 1cy). - Removed JFPU01 and JFPX from the list of resources consumed by pure float/vector loads (no MMX). I verified with llvm-exegesis that pure XMM/YMM loads are no-pipe. Those are dispatched to the FPU but not really issues on JFPU01. Differential Revision: https://reviews.llvm.org/D68871 llvm-svn: 374765		2019-10-14 11:12:18 +00:00
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AArch64	[llvm-mca][scheduler-stats] Print issued micro opcodes per cycle. NFCI	2019-04-08 16:05:54 +00:00
ARM	[MCA] Show aggregate over Average Wait times for the whole snippet (PR43219)	2019-10-10 14:46:21 +00:00
SystemZ	[MCA] Show aggregate over Average Wait times for the whole snippet (PR43219)	2019-10-10 14:46:21 +00:00
X86	[X86][BtVer2] Improved latency and throughput of float/vector loads and stores.	2019-10-14 11:12:18 +00:00
invalid_input_file_name.test	Replace unused output filenames with /dev/null in tests	2018-07-02 18:16:44 +00:00
lit.local.cfg	[lit] Delete empty lines at the end of lit.local.cfg NFC	2019-06-17 09:51:07 +00:00