260 lines
8.7 KiB
C++
260 lines
8.7 KiB
C++
//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Sparc implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcFrameLowering.h"
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#include "SparcInstrInfo.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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static cl::opt<bool>
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DisableLeafProc("disable-sparc-leaf-proc",
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cl::init(false),
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cl::desc("Disable Sparc leaf procedure optimization."),
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cl::Hidden);
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SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
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ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
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void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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int NumBytes,
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unsigned ADDrr,
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unsigned ADDri) const {
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DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
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if (NumBytes >= -4096 && NumBytes < 4096) {
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BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
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.addReg(SP::O6).addImm(NumBytes);
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return;
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}
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// Emit this the hard way. This clobbers G1 which we always know is
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// available here.
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if (NumBytes >= 0) {
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// Emit nonnegative numbers with sethi + or.
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// sethi %hi(NumBytes), %g1
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// or %g1, %lo(NumBytes), %g1
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// add %sp, %g1, %sp
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HI22(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
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.addReg(SP::G1).addImm(LO10(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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return ;
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}
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// Emit negative numbers with sethi + xor.
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// sethi %hix(NumBytes), %g1
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// xor %g1, %lox(NumBytes), %g1
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// add %sp, %g1, %sp
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BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HIX22(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
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.addReg(SP::G1).addImm(LOX10(NumBytes));
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BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
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.addReg(SP::O6).addReg(SP::G1);
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}
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void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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unsigned SAVEri = SP::SAVEri;
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unsigned SAVErr = SP::SAVErr;
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if (FuncInfo->isLeafProc()) {
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if (NumBytes == 0)
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return;
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SAVEri = SP::ADDri;
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SAVErr = SP::ADDrr;
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}
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NumBytes = -MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes);
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emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
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// Emit ".cfi_def_cfa_register 30".
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unsigned CFIIndex =
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MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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// Emit ".cfi_window_save".
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CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
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unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
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// Emit ".cfi_register 15, 31".
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CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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void SparcFrameLowering::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (!hasReservedCallFrame(MF)) {
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MachineInstr &MI = *I;
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int Size = MI.getOperand(0).getImm();
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
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}
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MBB.erase(I);
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}
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void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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const SparcInstrInfo &TII =
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*static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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assert(MBBI->getOpcode() == SP::RETL &&
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"Can only put epilog before 'retl' instruction!");
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if (!FuncInfo->isLeafProc()) {
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BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
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.addReg(SP::G0);
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return;
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}
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int NumBytes = (int) MFI->getStackSize();
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if (NumBytes == 0)
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return;
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NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes);
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emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
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}
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bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
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// Reserve call frame if there are no variable sized objects on the stack.
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return !MF.getFrameInfo()->hasVarSizedObjects();
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}
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
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}
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static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
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{
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
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if (MRI->isPhysRegUsed(reg))
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return false;
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for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
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if (MRI->isPhysRegUsed(reg))
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return false;
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return true;
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}
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bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
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{
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return !(MFI->hasCalls() // has calls
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|| MRI.isPhysRegUsed(SP::L0) // Too many registers needed
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|| MRI.isPhysRegUsed(SP::O6) // %SP is used
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|| hasFP(MF)); // need %FP
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}
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void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Remap %i[0-7] to %o[0-7].
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
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if (!MRI.isPhysRegUsed(reg))
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continue;
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unsigned mapped_reg = (reg - SP::I0 + SP::O0);
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assert(!MRI.isPhysRegUsed(mapped_reg));
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// Replace I register with O register.
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MRI.replaceRegWith(reg, mapped_reg);
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// Mark the reg unused.
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MRI.setPhysRegUnused(reg);
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}
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// Rewrite MBB's Live-ins.
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
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if (!MBB->isLiveIn(reg))
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continue;
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MBB->removeLiveIn(reg);
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MBB->addLiveIn(reg - SP::I0 + SP::O0);
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}
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}
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assert(verifyLeafProcRegUse(&MRI));
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#ifdef XDEBUG
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MF.verify(0, "After LeafProc Remapping");
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#endif
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}
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void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
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(MachineFunction &MF, RegScavenger *RS) const {
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if (!DisableLeafProc && isLeafProc(MF)) {
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SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
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MFI->setLeafProc(true);
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remapRegsForLeafProc(MF);
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}
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}
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