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luxufan 82c820b95c [RISCV] Enable the LocalStackSlotAllocation pass support 
For RISC-V, load/store(exclude vector load/store) instructions only
has a 12 bit immediate operand. If the offset is out-of-range, it
must make use of a temp register to make up this offset. If between
these offsets, they have a small(IsInt<12>) relative offset,
LocalStackSlotAllocation pass can find a value as frame base register's
value, and replace the origin offset with this register's value plus
the relative offset.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D98101
 		2022-10-19 16:15:14 +08:00
..
AsmParser [RISCV][CodeGen] add assertion to RISCVTargetStreamer getTargetStreamer() 2022-08-31 11:15:47 -07:00
Disassembler Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h` 2022-05-15 08:44:58 +08:00
MCTargetDesc [NFC][RISCV] Move getSEWLMULRatio function to header 2022-10-05 15:10:53 +01:00
TargetInfo [RISCV] Re-enable JIT support 2022-08-11 11:41:02 +02:00
CMakeLists.txt [RISCV] Add a RISCV specific CodeGenPrepare pass. 2022-07-14 10:20:59 -07:00
RISCV.h [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
RISCV.td [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVAsmPrinter.cpp [RISC-V][HWASAN] Fold variable into assert 2022-08-29 00:32:37 +02:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVCodeGenPrepare.cpp [RISCV] isImpliedByDomCondition returns an Optional<bool> not a bool. 2022-08-12 22:21:05 -07:00
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Avoid redundant branch-to-branch when expanding cmpxchg 2022-08-17 13:49:15 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVFrameLowering.cpp [RISCV] Pass the destination register to getVLENFactoredAmount instead of returning it. NFC 2022-10-03 10:59:35 -07:00
RISCVFrameLowering.h [RISCV] Enable the LocalStackSlotAllocation pass support 2022-10-19 16:15:14 +08:00
RISCVGatherScatterLowering.cpp [RISCV] Extend strided load/store pattern matching to non-loop cases 2022-09-27 12:56:58 -07:00
RISCVISelDAGToDAG.cpp [RISCV] Use hasAllWUsers to recover XORI/ORI 2022-10-10 14:16:50 +08:00
RISCVISelDAGToDAG.h [RISCV] Support peephole optimization to fold vmerge.vvm that has tail agnostic policy and unmasked intrinsics. 2022-09-21 10:56:37 +08:00
RISCVISelLowering.cpp [RISCV] Add an early out to lowerVECTOR_SHUFFLEAsVSlidedown. NFC 2022-10-18 21:35:15 -07:00
RISCVISelLowering.h [RISCV] Disallow scale for scatter/gather 2022-09-22 15:31:26 -07:00
RISCVInsertVSETVLI.cpp [RISCV] Use mask/tail agnostic if tied source is IMPLICIT_DEF regardless of the policy operand. 2022-10-11 16:40:16 -07:00
RISCVInstrFormats.td [RISCV] Support mask policy for RVV IR intrinsics. 2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp [MachineCombiner][RISCV] Enable MachineCombiner for RISCV 2022-10-18 18:56:32 +03:00
RISCVInstrInfo.h [MachineCombiner][RISCV] Enable MachineCombiner for RISCV 2022-10-18 18:56:32 +03:00
RISCVInstrInfo.td [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVInstrInfoA.td [RISCV] Add target feature to force-enable atomics 2022-08-09 16:04:46 +02:00
RISCVInstrInfoC.td [RISCV] : Add support for simm10_lsb0000nonzero operand. 2022-08-26 14:37:37 +08:00
RISCVInstrInfoD.td [RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*. 2022-09-12 09:37:28 -07:00
RISCVInstrInfoF.td [RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*. 2022-09-12 09:37:28 -07:00
RISCVInstrInfoM.td [RISCV][Clang] Add support for Zmmul extension 2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td [RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC 2022-10-14 12:11:55 -07:00
RISCVInstrInfoVPseudos.td [RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC 2022-10-14 12:11:55 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Use _TIED form of VFWADD(U)_WV/VFWSUB(U)_WV to avoid early clobber. 2022-10-03 21:44:08 -07:00
RISCVInstrInfoVVLPatterns.td [RISCV] Add isel patterns for vmacc, vnmsac. 2022-10-12 09:19:01 +08:00
RISCVInstrInfoZb.td [RISCV] Add missing scheduler classes to Zbkb and Zbkx instructions. 2022-09-23 21:38:42 -07:00
RISCVInstrInfoZfh.td [RISCV] Rename WriteFALU* and ReadFALU* to WriteFAdd*/ReadFAdd*. 2022-09-12 09:37:28 -07:00
RISCVInstrInfoZicbo.td [RISCV][NFC] Fix typo in comment in RISCVInstrInfoZicbo.td 2022-09-01 13:49:55 +01:00
RISCVInstrInfoZk.td
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RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [RISCV] Pre-RA expand pseudos pass 2022-07-31 23:19:00 +02:00
RISCVMachineFunctionInfo.cpp [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
RISCVMachineFunctionInfo.h [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
RISCVMacroFusion.cpp [RISCV] Be more strict about LUI+ADDI macrofusion pre-RA. 2022-08-21 10:58:15 -07:00
RISCVMacroFusion.h [RISCV] Add macrofusion infrastructure and one example usage. 2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp [RISCV] Fix wrong register rename for store value during make-compressible optimization 2022-07-08 18:07:17 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Fix operand number in debug message in RISCVMergeBaseOffset. 2022-08-02 15:27:23 -07:00
RISCVRedundantCopyElimination.cpp [RISCV] Use analyzeBranch in RISCVRedundantCopyElimination. 2022-08-29 09:05:53 -07:00
RISCVRegisterBankInfo.cpp [Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC) 2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp [RISCV] Enable the LocalStackSlotAllocation pass support 2022-10-19 16:15:14 +08:00
RISCVRegisterInfo.h [RISCV] Enable the LocalStackSlotAllocation pass support 2022-10-19 16:15:14 +08:00
RISCVRegisterInfo.td [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
RISCVSExtWRemoval.cpp [RISCV] Teach SExtWRemoval to recognize sign extended values that come from arguments. 2022-10-04 15:39:10 -07:00
RISCVSchedRocket.td [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVSchedSiFive7.td [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVSchedule.td [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVScheduleV.td [RISCV] Rename ReadVIALUCV->ReadVICALUV to match WriteVICALUV. NFC 2022-10-14 12:11:55 -07:00
RISCVScheduleZb.td [RISCV] Rename RISCVScheduleB.td to RISCVScheduleZb.td. NFC 2022-09-23 21:38:42 -07:00
RISCVSubtarget.cpp [RISCV] Enable fixed length vectors and loop vectorization with same 2022-08-26 14:45:23 -07:00
RISCVSubtarget.h [RISCV] Add basic support for the sifive-7-series short forward branch optimization. 2022-10-17 13:56:22 -07:00
RISCVSystemOperands.td
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RISCVTargetMachine.cpp [MachineCombiner][RISCV] Enable MachineCombiner for RISCV 2022-10-18 18:56:32 +03:00
RISCVTargetMachine.h [llvm] Remove redundaunt virtual specifiers (NFC) 2022-07-24 21:50:35 -07:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [RISCV] Correct RISCVTTIImpl::getRegUsageForType for vectors of pointers. 2022-10-14 11:34:12 -07:00
RISCVTargetTransformInfo.h [RISCV] Rename getVectorImmCost to getStoreImmCost [nfc] 2022-09-27 08:22:13 -07:00