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llvm-project/llvm/lib/Target/VE
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Kazushi (Jam) Marukawa 0278c9ceb6 [VE] Change the way to lower select 
Change to use VEISD::CMOV in combineSelect for better optimization.
Support VEISD::CMOV in combineTRUNCATE also to optimize trancate.
Merge functions to handle condition codes to VE.h.  And add basic
CMOV patterns to VEInstrInfo.td.  Update regression tests also.

Reviewed By: efocht

Differential Revision: https://reviews.llvm.org/D135878
 		2022-10-15 08:49:36 +09:00
..
AsmParser
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Disassembler Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h` 2022-05-15 08:44:58 +08:00
MCTargetDesc [CodeGen] Move instruction predicate verification to emitInstruction 2022-07-14 09:33:28 +01:00
TargetInfo
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CMakeLists.txt
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LVLGen.cpp
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VE.h [VE] Change the way to lower select 2022-10-15 08:49:36 +09:00
VE.td [TableGen] Add useDeprecatedPositionallyEncodedOperands option. 2022-09-24 09:40:45 -04:00
VEAsmPrinter.cpp [VE] Support inlineasm memory operand 2022-08-23 13:44:03 +09:00
VECallingConv.td
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VECustomDAG.cpp [llvm] Use value_or instead of getValueOr (NFC) 2022-06-18 23:07:11 -07:00
VECustomDAG.h [VE] v512|256 f32|64 fneg isel and tests 2022-03-16 11:31:26 +01:00
VEFrameLowering.cpp
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VEFrameLowering.h [llvm] Use std::size instead of llvm::array_lengthof 2022-09-08 09:01:53 -06:00
VEISelDAGToDAG.cpp [VE] Change the way to lower select 2022-10-15 08:49:36 +09:00
VEISelLowering.cpp [VE] Change the way to lower select 2022-10-15 08:49:36 +09:00
VEISelLowering.h [VE] Change the way to lower select 2022-10-15 08:49:36 +09:00
VEInstrBuilder.h
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VEInstrFormats.td
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VEInstrInfo.cpp [VE] Support load/store/spill of vector mask registers 2022-07-19 10:29:21 +09:00
VEInstrInfo.h
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VEInstrInfo.td [VE] Change the way to lower select 2022-10-15 08:49:36 +09:00
VEInstrIntrinsicVL.gen.td [VE] Support more intrinsics 2022-03-14 19:17:15 +09:00
VEInstrIntrinsicVL.td [VE] Support more intrinsics 2022-03-14 19:17:15 +09:00
VEInstrPatternsVec.td [VE] Support load/store/spill of vector mask registers 2022-07-19 10:29:21 +09:00
VEInstrVec.td [VE] Support load/store/spill of vector mask registers 2022-07-19 10:29:21 +09:00
VEMCInstLower.cpp
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VEMachineFunctionInfo.cpp llvm-reduce: Add cloning of target MachineFunctionInfo 2022-06-07 10:14:48 -04:00
VEMachineFunctionInfo.h llvm-reduce: Add cloning of target MachineFunctionInfo 2022-06-07 10:14:48 -04:00
VERegisterInfo.cpp [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
VERegisterInfo.h [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
VERegisterInfo.td [RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI 2022-08-24 14:16:20 +00:00
VESubtarget.cpp
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VESubtarget.h
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VETargetMachine.cpp [llvm] Use value_or instead of getValueOr (NFC) 2022-06-18 23:07:11 -07:00
VETargetMachine.h
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VETargetTransformInfo.h [VE] v256i32|64 reduction isel and tests 2022-03-14 11:10:38 +01:00
VVPISelLowering.cpp [llvm] Use value instead of getValue (NFC) 2022-07-13 23:11:56 -07:00
VVPInstrInfo.td [VE] v512|256 f32|64 fneg isel and tests 2022-03-16 11:31:26 +01:00
VVPInstrPatternsVec.td [VE] v512|256 f32|64 fneg isel and tests 2022-03-16 11:31:26 +01:00
VVPNodes.def [VE] v512|256 f32|64 fneg isel and tests 2022-03-16 11:31:26 +01:00