llvm-project/llvm/test/CodeGen/VE
Peter Rong c2e7c9cb33 [CodeGen] Using ZExt for extractelement indices.
In https://github.com/llvm/llvm-project/issues/57452, we found that IRTranslator is translating `i1 true` into `i32 -1`.
This is because IRTranslator uses SExt for indices.

In this fix, we change the expected behavior of extractelement's index, moving from SExt to ZExt.
This change includes both documentation, SelectionDAG and IRTranslator.
We also included a test for AMDGPU, updated tests for AArch64, Mips, PowerPC, RISCV, VE, WebAssembly and X86

This patch fixes issue #57452.

Differential Revision: https://reviews.llvm.org/D132978
2022-10-15 15:45:35 -07:00
..
Packed [VE] v512|256 f32|64 fneg isel and tests 2022-03-16 11:31:26 +01:00
Scalar [VE] Change the way to lower select 2022-10-15 08:49:36 +09:00
VELIntrinsics [VE] Support more intrinsics 2022-03-14 19:17:15 +09:00
Vector [CodeGen] Using ZExt for extractelement indices. 2022-10-15 15:45:35 -07:00
lit.local.cfg