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llvm-project/llvm/lib/Target/AArch64
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Simon Wallis 8ee1419ab6 [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 
Implement AArch64 variant of shouldCoalesce() to detect a known failing case
and prevent the coalescing of a 32-bit copy into a 64-bit sign-extending load.

Do not coalesce in the following case:
COPY where source is bottom 32 bits of a 64-register,
and destination is a 32-bit subregister of a 64-bit register,
ie it causes the rest of the register to be implicitly set to zero.

A mir test has been added.

In the test case, the 32-bit copy implements a 32 to 64 bit zero extension
and relies on the upper 32 bits being zeroed.

Coalescing to the result of the 64-bit load meant overwriting
the upper 32 bits incorrectly when the loaded byte was negative.

Reviewed By: john.brawn

Differential Revision: https://reviews.llvm.org/D85956
 		2020-09-08 08:04:52 +01:00
..
AsmParser [AArch64] Add asm directives for the remaining SEH unwind codes 2020-09-03 11:12:01 +03:00
Disassembler [AArch64] Emit warning when disassembling unpredictable LDRAA and LDRAB 2020-06-25 15:56:36 +01:00
GISel Revert "Revert "[GlobalISel] Fold xor(cmp(pred, _, _), 1) -> cmp(inverse(pred), _, _)" (and dependent patch "Optimize away a Not feeding a brcond by using tbz instead of tbnz.")" 2020-09-01 14:29:04 -07:00
MCTargetDesc [AArch64] Add asm directives for the remaining SEH unwind codes 2020-09-03 11:12:01 +03:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Utils [ARM, AArch64] Fix a comment typo. NFC. 2020-08-06 09:23:45 +03:00
AArch64.h [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. 2020-06-12 07:34:33 +01:00
AArch64.td [ARM] Add Cortex-A78 and Cortex-X1 Support for Clang and LLVM 2020-07-10 18:24:11 +01:00
AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp [AArch64] Update a code comment incorrectly referring to zero_reg. NFC 2020-08-20 14:36:59 +02:00
AArch64AsmPrinter.cpp [DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructions 2020-06-22 16:01:12 +01:00
AArch64BranchTargets.cpp [AArch64] Fix BTI instruction emission. 2020-06-15 15:04:36 +02:00
AArch64CallingConvention.cpp [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CallingConvention.h
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AArch64CallingConvention.td [Alignment][NFC] Use Align for TargetCallingConv::OrigAlign 2020-06-25 13:21:22 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00
AArch64CollectLOH.cpp [AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg 2020-06-01 16:00:55 -07:00
AArch64Combine.td [GlobalISel] Add combine for (x & mask) -> x when (x & mask) == x 2020-08-19 10:20:57 -07:00
AArch64CompressJumpTables.cpp [Alignment][NFC] Deprecate Align::None() 2020-01-24 12:53:58 +01:00
AArch64CondBrTuning.cpp [AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14] 2020-04-22 17:03:40 -07:00
AArch64ConditionOptimizer.cpp MachineBasicBlock::updateTerminator now requires an explicit layout successor. 2020-06-06 22:30:51 -04:00
AArch64ConditionalCompares.cpp DomTree: Remove getChildren() accessor 2020-07-06 21:58:11 +02:00
AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp [SVE] Fix invalid assert in expand_DestructiveOp. 2020-07-04 09:21:40 +00:00
AArch64FalkorHWPFFix.cpp Prefix some AArch64/ARM passes with "aarch64-"/"arm-" 2020-07-27 11:00:39 -07:00
AArch64FastISel.cpp [FastISel] update to use intrinsic's isCommutative(); NFC 2020-08-30 11:36:41 -04:00
AArch64FrameLowering.cpp Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64FrameLowering.h [AArch64][SVE] Add missing unwind info for SVE registers. 2020-08-04 11:47:06 +01:00
AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp [SVE] Make ElementCount members private 2020-08-28 14:43:53 +01:00
AArch64ISelLowering.cpp [AArch64][SVE] Add lowering for rounding operations 2020-09-04 11:16:57 -04:00
AArch64ISelLowering.h [AArch64][SVE] Add lowering for rounding operations 2020-09-04 11:16:57 -04:00
AArch64InstrAtomics.td DAG: Use TargetConstant for FENCE operands 2020-01-02 17:16:10 -05:00
AArch64InstrFormats.td [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics 2020-08-27 18:43:16 +01:00
AArch64InstrGISel.td [AArch64][GlobalISel] Add G_EXT and select ext using it 2020-06-15 12:20:59 -07:00
AArch64InstrInfo.cpp Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64InstrInfo.h [AArch64][SVE] NFC: Rename isOrig -> isReverseInstr 2020-07-02 17:01:15 +01:00
AArch64InstrInfo.td [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics 2020-08-27 18:43:16 +01:00
AArch64LoadStoreOptimizer.cpp [AArch64] Fix ldst-opt of multiple disjunct subregs. 2020-06-08 20:18:24 +01:00
AArch64MCInstLower.cpp
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AArch64MCInstLower.h
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AArch64MachineFunctionInfo.cpp MachineFunctionInfo for AArch64 in MIR 2020-04-17 15:16:59 -07:00
AArch64MachineFunctionInfo.h Revert "Revert "Reapply D70800: Fix AArch64 AAPCS frame record chain"" 2020-09-01 19:29:03 +00:00
AArch64MacroFusion.cpp
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AArch64MacroFusion.h
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp [AArch64] Don't promote constants with float ConstantExpr. 2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 2020-09-08 08:04:52 +01:00
AArch64RegisterInfo.h [AARCH64][RegisterCoalescer] clang miscompiles zero-extension to long long 2020-09-08 08:04:52 +01:00
AArch64RegisterInfo.td [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64SIMDInstrOpt.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
AArch64SLSHardening.cpp [NFC] Clean up uses of MachineModuleInfoWrapperPass 2020-07-01 09:45:05 -07:00
AArch64SVEInstrInfo.td [AArch64][SVE] Add lowering for rounding operations 2020-09-04 11:16:57 -04:00
AArch64SchedA53.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
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AArch64SchedCyclone.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td [AArch64] Add BIT/BIF support. 2020-02-14 14:19:39 +00:00
AArch64SchedKryo.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td [AArch64] Add BIT/BIF support. 2020-02-14 14:19:39 +00:00
AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedThunderX.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX2T99.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td [AARch64] Add Marvell ThunderX3T110 support 2020-05-13 16:58:51 -07:00
AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp [CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize 2020-08-11 12:17:10 +01:00
AArch64SelectionDAGInfo.h [Alignment][NFC] Migrate SelectionDAGTargetInfo::EmitTargetCodeForMemset to Align 2020-06-30 12:46:26 +00:00
AArch64SpeculationHardening.cpp
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AArch64StackOffset.h [AArch64][SVE] Fix CFA calculation in presence of SVE objects. 2020-08-04 11:47:06 +01:00
AArch64StackTagging.cpp [ValueTracking] Remove AllocaForValue parameter 2020-07-30 18:48:34 -07:00
AArch64StackTaggingPreRA.cpp
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AArch64StorePairSuppress.cpp Add OffsetIsScalable to getMemOperandWithOffset 2020-02-18 15:53:29 +00:00
AArch64Subtarget.cpp [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
AArch64Subtarget.h [X86][MC][Target] Initial backend support a tune CPU to support -mtune 2020-08-14 15:31:50 -07:00
AArch64SystemOperands.td [AArch64] Remove inexistent system register ERXTS_EL1 2020-04-29 16:43:48 +01:00
AArch64TargetMachine.cpp Reland [SimplifyCFG][LoopRotate] SimplifyCFG: disable common instruction hoisting by default, enable late in pipeline 2020-09-08 00:24:03 +03:00
AArch64TargetMachine.h Support addrspacecast initializers with isNoopAddrSpaceCast 2020-07-31 10:42:43 -04:00
AArch64TargetObjectFile.cpp [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile 2020-03-20 21:57:34 -07:00
AArch64TargetObjectFile.h [llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation 2020-06-10 11:34:16 -07:00
AArch64TargetTransformInfo.cpp [Analysis] TTI: Add CastContextHint for getCastInstrCost 2020-07-29 13:32:53 +01:00
AArch64TargetTransformInfo.h [AArch64][SVE] Allow vector of pointers as legal type for masked load/store. 2020-07-31 17:30:23 -07:00
CMakeLists.txt [AArch64] Introduce AArch64SLSHardeningPass, implementing hardening of RET and BR instructions. 2020-06-11 07:51:17 +01:00
LLVMBuild.txt
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SVEInstrFormats.td [AArch64][SVE] Add lowering for llvm fceil 2020-08-26 15:59:44 -04:00
SVEIntrinsicOpts.cpp [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest 2020-08-14 07:57:21 +01:00