llvm-project/llvm/test/Analysis/CostModel/AArch64
David Sherwood 7b64765cd1 [SVE] Fix TypeSize related warnings with IR truncates of scalable vectors
In getCastInstrCost when the instruction is a truncate we were relying
upon the implicit TypeSize -> uint64_t cast when asking if a given type
has the same size as a legal integer. I've changed the code to only
ask the question if the type is fixed length.

I have also changed InstCombinerImpl::SimplifyDemandedUseBits to bail
out for now if the type is a scalable vector.

I've added the following new tests:

  Analysis/CostModel/AArch64/sve-trunc.ll
  Transforms/InstCombine/AArch64/sve-trunc.ll

for both of these fixes.

Differential revision: https://reviews.llvm.org/D86432
2020-08-25 09:17:56 +01:00
..
aggregates.ll [AArch64] Add getCFInstrCost, treat branches as free for throughput. 2020-06-30 20:34:04 +01:00
bswap.ll
cast.ll [AArch64] Add getCFInstrCost, treat branches as free for throughput. 2020-06-30 20:34:04 +01:00
cmp.ll [AArch64] Add getCFInstrCost, treat branches as free for throughput. 2020-06-30 20:34:04 +01:00
div.ll
div_cte.ll
free-widening-casts.ll
gep.ll
kryo.ll
lit.local.cfg
select.ll [AArch64] Add getCFInstrCost, treat branches as free for throughput. 2020-06-30 20:34:04 +01:00
shuffle-broadcast.ll [AArch64] Add getCFInstrCost, treat branches as free for throughput. 2020-06-30 20:34:04 +01:00
shuffle-select.ll
shuffle-transpose.ll
store.ll [AArch64] Add getCFInstrCost, treat branches as free for throughput. 2020-06-30 20:34:04 +01:00
sve-bitcast.ll [NFC][documentation] clarify comment in test 2020-08-21 14:30:47 -07:00
sve-fixed-length.ll [SVE] Add flag to specify SVE register size, using this to calculate legal vector types. 2020-06-18 12:11:16 +00:00
sve-trunc.ll [SVE] Fix TypeSize related warnings with IR truncates of scalable vectors 2020-08-25 09:17:56 +01:00
vector-reduce.ll