142 lines
3.9 KiB
LLVM
142 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBKB
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define i32 @pack_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: pack_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 16
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; RV32I-NEXT: srli a0, a0, 16
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; RV32I-NEXT: slli a1, a1, 16
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBKB-LABEL: pack_i32:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: pack a0, a0, a1
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; RV32ZBKB-NEXT: ret
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%shl = and i32 %a, 65535
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%shl1 = shl i32 %b, 16
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%or = or i32 %shl1, %shl
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ret i32 %or
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}
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @pack_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: pack_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a1, a2
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; CHECK-NEXT: ret
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%shl = and i64 %a, 4294967295
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%shl1 = shl i64 %b, 32
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%or = or i64 %shl1, %shl
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ret i64 %or
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}
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; As we are not matching directly i64 code patterns on RV32 some i64 patterns
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; don't have yet any matching bit manipulation instructions on RV32.
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; This test is presented here in case future expansions of the Bitmanip
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; extensions introduce instructions suitable for this pattern.
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define i64 @packu_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: packu_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mv a0, a1
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; CHECK-NEXT: mv a1, a3
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; CHECK-NEXT: ret
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%shr = lshr i64 %a, 32
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%shr1 = and i64 %b, -4294967296
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%or = or i64 %shr1, %shr
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ret i64 %or
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}
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define i32 @packh_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: packh_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: slli a1, a1, 24
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; RV32I-NEXT: srli a1, a1, 16
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBKB-LABEL: packh_i32:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: packh a0, a0, a1
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; RV32ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = shl i32 %b, 8
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%shl = and i32 %and1, 65280
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: packh_i32_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: andi a1, a1, 255
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBKB-LABEL: packh_i32_2:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: packh a0, a0, a1
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; RV32ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = and i32 %b, 255
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%shl = shl i32 %and1, 8
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i64 @packh_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: packh_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: slli a1, a2, 24
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; RV32I-NEXT: srli a1, a1, 16
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV32ZBKB-LABEL: packh_i64:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: packh a0, a0, a2
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; RV32ZBKB-NEXT: li a1, 0
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; RV32ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = shl i64 %b, 8
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%shl = and i64 %and1, 65280
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%or = or i64 %shl, %and
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ret i64 %or
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}
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define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: packh_i64_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 255
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; RV32I-NEXT: andi a1, a2, 255
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; RV32I-NEXT: slli a1, a1, 8
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: li a1, 0
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; RV32I-NEXT: ret
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;
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; RV32ZBKB-LABEL: packh_i64_2:
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; RV32ZBKB: # %bb.0:
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; RV32ZBKB-NEXT: packh a0, a0, a2
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; RV32ZBKB-NEXT: li a1, 0
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; RV32ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = and i64 %b, 255
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%shl = shl i64 %and1, 8
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%or = or i64 %shl, %and
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ret i64 %or
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}
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