124 lines
3.2 KiB
LLVM
124 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64ZBKB
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define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: pack_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: slliw a1, a1, 16
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packw a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%shl = and i32 %a, 65535
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%shl1 = shl i32 %b, 16
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%or = or i32 %shl1, %shl
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ret i32 %or
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}
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define i64 @pack_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: pack_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: pack a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%shl = and i64 %a, 4294967295
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%shl1 = shl i64 %b, 32
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%or = or i64 %shl1, %shl
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ret i64 %or
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}
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define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: packh_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srli a1, a1, 48
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = shl i32 %b, 8
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%shl = and i32 %and1, 65280
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: packh_i32_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: andi a1, a1, 255
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i32_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = and i32 %b, 255
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%shl = shl i32 %and1, 8
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i64 @packh_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: packh_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srli a1, a1, 48
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = shl i64 %b, 8
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%shl = and i64 %and1, 65280
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%or = or i64 %shl, %and
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ret i64 %or
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}
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define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: packh_i64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: andi a1, a1, 255
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i64_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = and i64 %b, 255
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%shl = shl i64 %and1, 8
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%or = or i64 %shl, %and
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ret i64 %or
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}
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